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/**
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******************************************************************************
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* @file stm32f4x7_eth_conf.h
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* @author MCD Application Team
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* @version V1.1.0
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* @date 31-July-2013
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* @brief Configuration file for the STM32F4x7 Ethernet driver.
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>
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*
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* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
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* You may not use this file except in compliance with the License.
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* You may obtain a copy of the License at:
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*
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* http://www.st.com/software_license_agreement_liberty_v2
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __STM32F4x7_ETH_CONF_H
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#define __STM32F4x7_ETH_CONF_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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#include "stm32f4xx.h"
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/* Exported types ------------------------------------------------------------*/
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/* Exported constants --------------------------------------------------------*/
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/* Uncomment the line below when using time stamping and/or IPv4 checksum offload */
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#define USE_ENHANCED_DMA_DESCRIPTORS
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/* Uncomment the line below if you want to use user defined Delay function
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(for precise timing), otherwise default _eth_delay_ function defined within
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the Ethernet driver is used (less precise timing) */
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#define USE_Delay
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#ifdef USE_Delay
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//#include "main.h" /* Header file where the Delay function prototype is exported */
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//#define _eth_delay_ Delay /* User can provide more timing precise _eth_delay_ function
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// in this example Systick is configured with an interrupt every 10 ms*/
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extern void SysTimer_delay_ms(uint32_t ms);
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#define _eth_delay_(ms) {SysTimer_delay_ms((uint32_t)ms);}
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#else
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#define _eth_delay_ ETH_Delay /* Default _eth_delay_ function with less precise timing */
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#endif
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/*This define allow to customize configuration of the Ethernet driver buffers */
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#define CUSTOM_DRIVER_BUFFERS_CONFIG
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#ifdef CUSTOM_DRIVER_BUFFERS_CONFIG
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/* Redefinition of the Ethernet driver buffers size and count */
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#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */
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#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */
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#define ETH_RXBUFNB 4 /* 4 Rx buffers of size ETH_RX_BUF_SIZE */
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#define ETH_TXBUFNB 4 /* 4 Tx buffers of size ETH_TX_BUF_SIZE */
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#endif
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/* PHY configuration section **************************************************/
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#ifdef USE_Delay
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/* PHY Reset delay */
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#define PHY_RESET_DELAY ((uint32_t)0x00000FFF)
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/* PHY Configuration delay */
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#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFF)
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/* Delay when writing to Ethernet registers*/
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#define ETH_REG_WRITE_DELAY ((uint32_t)0x00000001)
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#else
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/* PHY Reset delay */
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#define PHY_RESET_DELAY ((uint32_t)0x000FFFFF)
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/* PHY Configuration delay */
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#define PHY_CONFIG_DELAY ((uint32_t)0x00FFFFFF)
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/* Delay when writing to Ethernet registers*/
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#define ETH_REG_WRITE_DELAY ((uint32_t)0x0000FFFF)
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#endif
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/******************* PHY Extended Registers section : ************************/
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/* These values are relatives to DP83848 PHY and change from PHY to another,
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so the user have to update this value depending on the used external PHY */
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/* The DP83848 PHY status register */
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#define PHY_SR ((uint16_t)0x10) /* PHY status register Offset */
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#define PHY_SPEED_STATUS ((uint16_t)0x0002) /* PHY Speed mask */
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#define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /* PHY Duplex mask */
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/* The DP83848 PHY: MII Interrupt Control Register */
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#define PHY_MICR ((uint16_t)0x11) /* MII Interrupt Control Register */
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#define PHY_MICR_INT_EN ((uint16_t)0x0002) /* PHY Enable interrupts */
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#define PHY_MICR_INT_OE ((uint16_t)0x0001) /* PHY Enable output interrupt events */
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/* The DP83848 PHY: MII Interrupt Status and Misc. Control Register */
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#define PHY_MISR ((uint16_t)0x12) /* MII Interrupt Status and Misc. Control Register */
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#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020) /* Enable Interrupt on change of link status */
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#define PHY_LINK_STATUS ((uint16_t)0x2000) /* PHY link status interrupt mask */
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/* Note : Common PHY registers are defined in stm32f4x7_eth.h file */
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/* Exported macro ------------------------------------------------------------*/
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/* Exported functions ------------------------------------------------------- */
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#ifdef __cplusplus
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}
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#endif
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#endif /* __STM32F4x7_ETH_CONF_H */
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/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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