Project

General

Profile

Place the required xilinx / digilent files on the Aimagin... » board 1.0.xml

Johan Henning, 16 Feb 2023 17:59

 
1
<?xml version="1.0" encoding="UTF-8" standalone="no"?> 
2
<board schema_version="2.0" vendor="digilentinc.com" name="zybo-z7-20" display_name="Zybo Z7-20" url="https://reference.digilentinc.com/reference/programmable-logic/zybo-z7/start" preset_file="preset.xml" >
3
<compatible_board_revisions>
4
  <revision id="0">B.2</revision>
5
</compatible_board_revisions>
6
<file_version>1.0</file_version>
7
<description>Zybo Z7-20</description>
8
<components>
9
  <component name="part0" display_name="Zybo Z7-20" type="fpga" part_name="xc7z020clg400-1" pin_map_file="part0_pins.xml" vendor="xilinx" spec_url="https://reference.digilentinc.com/reference/programmable-logic/zybo-z7/start">
10
    <interfaces>
11
      <interface mode="master" name="btns_4bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="btns_4bits" preset_proc="push_buttons_4bits_preset">
12
        <port_maps>
13
          <port_map logical_port="TRI_I" physical_port="btns_4bits_tri_i" dir="in" left="3" right="0"> 
14
            <pin_maps>
15
              <pin_map port_index="0" component_pin="btns_4bits_tri_i_0"/> 
16
              <pin_map port_index="1" component_pin="btns_4bits_tri_i_1"/> 
17
              <pin_map port_index="2" component_pin="btns_4bits_tri_i_2"/> 
18
              <pin_map port_index="3" component_pin="btns_4bits_tri_i_3"/> 
19
            </pin_maps>
20
          </port_map>
21
        </port_maps>
22
      </interface>
23
      <interface mode="master" name="leds_4bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="leds_4bits" preset_proc="led_4bits_preset">
24
        <port_maps>
25
          <port_map logical_port="TRI_O" physical_port="leds_4bits_tri_o" dir="out" left="3" right="0"> 
26
            <pin_maps>
27
              <pin_map port_index="0" component_pin="leds_4bits_tri_o_0"/> 
28
              <pin_map port_index="1" component_pin="leds_4bits_tri_o_1"/> 
29
              <pin_map port_index="2" component_pin="leds_4bits_tri_o_2"/> 
30
              <pin_map port_index="3" component_pin="leds_4bits_tri_o_3"/> 
31
            </pin_maps>
32
          </port_map>
33
        </port_maps>
34
      </interface>
35
      <interface mode="master" name="ps7_fixedio" type="xilinx.com:display_processing_system7:fixedio_rtl:1.0" of_component="ps7_fixedio" preset_proc="ps7_preset"> 
36
      </interface>
37
      <interface mode="master" name="sws_4bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="sws_4bits" preset_proc="dip_switches_4bits_preset">
38
		<port_maps>
39
          <port_map logical_port="TRI_I" physical_port="sws_4bits_tri_i" dir="in" left="3" right="0"> 
40
            <pin_maps>
41
              <pin_map port_index="0" component_pin="sws_4bits_tri_i_0"/> 
42
              <pin_map port_index="1" component_pin="sws_4bits_tri_i_1"/> 
43
              <pin_map port_index="2" component_pin="sws_4bits_tri_i_2"/> 
44
              <pin_map port_index="3" component_pin="sws_4bits_tri_i_3"/> 
45
            </pin_maps>
46
          </port_map>
47
        </port_maps>
48
      </interface>
49
      <interface mode="slave" name="sys_clock" type="xilinx.com:signal:clock_rtl:1.0" of_component="sys_clock" preset_proc="sys_clock_preset">
50
        <port_maps>
51
          <port_map logical_port="CLK" physical_port="sys_clk" dir="in">
52
            <pin_maps>
53
              <pin_map port_index="0" component_pin="sys_clk"/> 
54
            </pin_maps>
55
          </port_map>
56
        </port_maps>
57
        <parameters>
58
          <parameter name="frequency" value="125000000" />
59
       </parameters>
60
      </interface>
61
	   
62
	  	  <interface mode="slave" name="hdmi_in" type="digilentinc.com:interface:tmds_rtl:1.0" of_component="hdmi_in" preset_proc="hdmi_in_preset">
63
        <preferred_ips>
64
			<preferred_ip vendor="digilentinc.com" library="ip" name="dvi2rgb" order="0"/>
65
		</preferred_ips>
66
		<port_maps>
67
          <port_map logical_port="CLK_P" physical_port="TMDS_IN_clk_p" dir="in">
68
            <pin_maps>
69
              <pin_map port_index="0" component_pin="TMDS_IN_clk_p"/> 
70
            </pin_maps>
71
          </port_map>
72
          <port_map logical_port="CLK_N" physical_port="TMDS_IN_clk_n" dir="in">
73
            <pin_maps>
74
              <pin_map port_index="0" component_pin="TMDS_IN_clk_n"/> 
75
            </pin_maps>
76
          </port_map>
77
          <port_map logical_port="DATA_P" physical_port="TMDS_IN_D_P" dir="in" left="2" right="0">
78
            <pin_maps>
79
              <pin_map port_index="0" component_pin="TMDS_IN_data_p_0"/> 
80
			  <pin_map port_index="1" component_pin="TMDS_IN_data_p_1"/> 
81
			  <pin_map port_index="2" component_pin="TMDS_IN_data_p_2"/> 
82
            </pin_maps>
83
          </port_map>
84
          <port_map logical_port="DATA_N" physical_port="TMDS_IN_D_N" dir="in" left="2" right="0">
85
            <pin_maps>
86
              <pin_map port_index="0" component_pin="TMDS_IN_data_n_0"/> 
87
			  <pin_map port_index="1" component_pin="TMDS_IN_data_n_1"/> 
88
			  <pin_map port_index="2" component_pin="TMDS_IN_data_n_2"/> 
89
            </pin_maps>
90
          </port_map>
91
        </port_maps>
92
      </interface>
93
	   <interface mode="master" name="hdmi_in_ddc" type="xilinx.com:interface:iic_rtl:1.0" of_component="hdmi_in" preset_proc="hdmi_in_preset">
94
        <description>HDMI DDC</description>
95
		<preferred_ips>
96
			<preferred_ip vendor="digilentinc.com" library="ip" name="dvi2rgb" order="0"/>
97
		</preferred_ips>
98
		<port_maps>
99
          <port_map logical_port="SDA_I" physical_port="hdmi_in_ddc_sda" dir="in">
100
            <pin_maps>
101
              <pin_map port_index="0" component_pin="hdmi_in_ddc_sda"/> 
102
            </pin_maps>
103
          </port_map>
104
          <port_map logical_port="SDA_O" physical_port="hdmi_in_ddc_sda" dir="out">
105
            <pin_maps>
106
              <pin_map port_index="0" component_pin="hdmi_in_ddc_sda"/> 
107
            </pin_maps>
108
          </port_map>
109
          <port_map logical_port="SDA_T" physical_port="hdmi_in_ddc_sda" dir="out">
110
            <pin_maps>
111
              <pin_map port_index="0" component_pin="hdmi_in_ddc_sda"/> 
112
            </pin_maps>
113
          </port_map>
114
          <port_map logical_port="SCL_I" physical_port="hdmi_in_ddc_scl" dir="in">
115
            <pin_maps>
116
              <pin_map port_index="0" component_pin="hdmi_in_ddc_scl"/> 
117
            </pin_maps>
118
          </port_map>
119
          <port_map logical_port="SCL_O" physical_port="hdmi_in_ddc_scl" dir="out">
120
            <pin_maps>
121
              <pin_map port_index="0" component_pin="hdmi_in_ddc_scl"/> 
122
            </pin_maps>
123
          </port_map>
124
          <port_map logical_port="SCL_T" physical_port="hdmi_in_ddc_scl" dir="out">
125
            <pin_maps>
126
              <pin_map port_index="0" component_pin="hdmi_in_ddc_scl"/> 
127
            </pin_maps>
128
          </port_map>
129
        </port_maps>
130
      </interface>
131
      <interface mode="master" name="hdmi_in_hpd_led" type="xilinx.com:interface:gpio_rtl:1.0" of_component="hdmi_in_hpd_led" preset_proc="output_1bit_preset">
132
        <port_maps>
133
          <port_map logical_port="TRI_O" physical_port="hdmi_rx_hpd" dir="out">
134
            <pin_maps>
135
              <pin_map port_index="0" component_pin="hdmi_rx_hpd"/> 
136
            </pin_maps>
137
          </port_map>
138
		  <port_map logical_port="TRI_I" physical_port="hdmi_rx_hpd" dir="in">
139
            <pin_maps>
140
              <pin_map port_index="0" component_pin="hdmi_rx_hpd"/> 
141
            </pin_maps>
142
          </port_map>
143
		  <port_map logical_port="TRI_T" physical_port="hdmi_rx_hpd" dir="out">
144
            <pin_maps>
145
              <pin_map port_index="0" component_pin="hdmi_rx_hpd"/> 
146
            </pin_maps>
147
          </port_map>
148
        </port_maps>
149
      </interface>
150
      <interface mode="master" name="hdmi_out" type="digilentinc.com:interface:tmds_rtl:1.0" of_component="hdmi_out">
151
        <description>HDMI Out</description>
152
		<preferred_ips>
153
			<preferred_ip vendor="digilentinc.com" library="ip" name="rgb2dvi" order="0"/>
154
		</preferred_ips>
155
		<port_maps>
156
          <port_map logical_port="CLK_P" physical_port="TMDS_OUT_clk_p" dir="out">
157
            <pin_maps>
158
              <pin_map port_index="0" component_pin="TMDS_OUT_clk_p"/> 
159
            </pin_maps>
160
          </port_map>
161
          <port_map logical_port="CLK_N" physical_port="TMDS_OUT_clk_n" dir="out">
162
            <pin_maps>
163
              <pin_map port_index="0" component_pin="TMDS_OUT_clk_n"/> 
164
            </pin_maps>
165
          </port_map>
166
          <port_map logical_port="DATA_P" physical_port="TMDS_OUT_D_P" dir="out" left="2" right="0">
167
            <pin_maps>
168
              <pin_map port_index="0" component_pin="TMDS_OUT_data_p_0"/> 
169
			  <pin_map port_index="1" component_pin="TMDS_OUT_data_p_1"/> 
170
			  <pin_map port_index="2" component_pin="TMDS_OUT_data_p_2"/> 
171
            </pin_maps>
172
          </port_map>
173
          <port_map logical_port="DATA_N" physical_port="TMDS_OUT_D_N" dir="out" left="2" right="0">
174
            <pin_maps>
175
              <pin_map port_index="0" component_pin="TMDS_OUT_data_n_0"/> 
176
			  <pin_map port_index="1" component_pin="TMDS_OUT_data_n_1"/> 
177
			  <pin_map port_index="2" component_pin="TMDS_OUT_data_n_2"/> 
178
            </pin_maps>
179
          </port_map>
180
        </port_maps>
181
      </interface>
182
      <interface mode="master" name="hdmi_out_hpd_led" type="xilinx.com:interface:gpio_rtl:1.0" of_component="hdmi_out_hpd_led" preset_proc="output_1bit_preset">
183
        <port_maps>
184
          <port_map logical_port="TRI_O" physical_port="hdmi_tx_hpd" dir="out">
185
            <pin_maps>
186
              <pin_map port_index="0" component_pin="hdmi_tx_hpd"/> 
187
            </pin_maps>
188
          </port_map>
189
		  <port_map logical_port="TRI_I" physical_port="hdmi_tx_hpd" dir="in">
190
            <pin_maps>
191
              <pin_map port_index="0" component_pin="hdmi_tx_hpd"/> 
192
            </pin_maps>
193
          </port_map>
194
		  <port_map logical_port="TRI_T" physical_port="hdmi_tx_hpd" dir="out">
195
            <pin_maps>
196
              <pin_map port_index="0" component_pin="hdmi_tx_hpd"/> 
197
            </pin_maps>
198
          </port_map>
199
        </port_maps>
200
      </interface>
201
	   
202
	  <interface mode="master" name="ja" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="ja">
203
        <port_maps>
204
          <port_map logical_port="PIN1_I" physical_port="JA1" dir="in"> 
205
            <pin_maps>
206
              <pin_map port_index="0" component_pin="JA1"/> 
207
			</pin_maps>
208
		  </port_map>
209
		  <port_map logical_port="PIN1_O" physical_port="JA1" dir="out"> 
210
            <pin_maps>
211
              <pin_map port_index="0" component_pin="JA1"/> 
212
			</pin_maps>
213
		  </port_map>
214
		  <port_map logical_port="PIN1_T" physical_port="JA1" dir="out"> 
215
            <pin_maps>
216
              <pin_map port_index="0" component_pin="JA1"/> 
217
			</pin_maps>
218
		  </port_map>
219
		  <port_map logical_port="PIN2_I" physical_port="JA2" dir="in"> 
220
            <pin_maps>
221
              <pin_map port_index="0" component_pin="JA2"/> 
222
			</pin_maps>
223
		  </port_map>
224
		  <port_map logical_port="PIN2_O" physical_port="JA2" dir="out"> 
225
            <pin_maps>
226
              <pin_map port_index="0" component_pin="JA2"/> 
227
			</pin_maps>
228
		  </port_map>
229
		  <port_map logical_port="PIN2_T" physical_port="JA2" dir="out"> 
230
            <pin_maps>
231
              <pin_map port_index="0" component_pin="JA2"/> 
232
			</pin_maps>
233
		  </port_map>
234
		  <port_map logical_port="PIN3_I" physical_port="JA3" dir="in"> 
235
            <pin_maps>
236
              <pin_map port_index="0" component_pin="JA3"/> 
237
			</pin_maps>
238
		  </port_map>
239
		  <port_map logical_port="PIN3_O" physical_port="JA3" dir="out"> 
240
            <pin_maps>
241
              <pin_map port_index="0" component_pin="JA3"/> 
242
			</pin_maps>
243
		  </port_map>
244
		  <port_map logical_port="PIN3_T" physical_port="JA3" dir="out"> 
245
            <pin_maps>
246
              <pin_map port_index="0" component_pin="JA3"/> 
247
			</pin_maps>
248
		  </port_map>
249
		  <port_map logical_port="PIN4_I" physical_port="JA4" dir="in"> 
250
            <pin_maps>
251
              <pin_map port_index="0" component_pin="JA4"/> 
252
			</pin_maps>
253
		  </port_map>
254
		  <port_map logical_port="PIN4_O" physical_port="JA4" dir="out"> 
255
            <pin_maps>
256
              <pin_map port_index="0" component_pin="JA4"/> 
257
			</pin_maps>
258
		  </port_map>
259
		  <port_map logical_port="PIN4_T" physical_port="JA4" dir="out"> 
260
            <pin_maps>
261
              <pin_map port_index="0" component_pin="JA4"/> 
262
			</pin_maps>
263
		  </port_map>
264
		  <port_map logical_port="PIN7_I" physical_port="JA7" dir="in"> 
265
            <pin_maps>
266
              <pin_map port_index="0" component_pin="JA7"/> 
267
			</pin_maps>
268
		  </port_map>
269
		  <port_map logical_port="PIN7_O" physical_port="JA7" dir="out"> 
270
            <pin_maps>
271
              <pin_map port_index="0" component_pin="JA7"/> 
272
			</pin_maps>
273
		  </port_map>
274
		  <port_map logical_port="PIN7_T" physical_port="JA7" dir="out"> 
275
            <pin_maps>
276
              <pin_map port_index="0" component_pin="JA7"/> 
277
			</pin_maps>
278
		  </port_map>
279
		  <port_map logical_port="PIN8_I" physical_port="JA8" dir="in"> 
280
            <pin_maps>
281
              <pin_map port_index="0" component_pin="JA8"/> 
282
			</pin_maps>
283
		  </port_map>
284
		  <port_map logical_port="PIN8_O" physical_port="JA8" dir="out"> 
285
            <pin_maps>
286
              <pin_map port_index="0" component_pin="JA8"/> 
287
			</pin_maps>
288
		  </port_map>
289
		  <port_map logical_port="PIN8_T" physical_port="JA8" dir="out"> 
290
            <pin_maps>
291
              <pin_map port_index="0" component_pin="JA8"/> 
292
			</pin_maps>
293
		  </port_map>
294
		  <port_map logical_port="PIN9_I" physical_port="JA9" dir="in"> 
295
            <pin_maps>
296
              <pin_map port_index="0" component_pin="JA9"/> 
297
			</pin_maps>
298
		  </port_map>
299
		  <port_map logical_port="PIN9_O" physical_port="JA9" dir="out"> 
300
            <pin_maps>
301
              <pin_map port_index="0" component_pin="JA9"/> 
302
			</pin_maps>
303
		  </port_map>
304
		  <port_map logical_port="PIN9_T" physical_port="JA9" dir="out"> 
305
            <pin_maps>
306
              <pin_map port_index="0" component_pin="JA9"/> 
307
			</pin_maps>
308
		  </port_map>
309
		  <port_map logical_port="PIN10_I" physical_port="JA10" dir="in"> 
310
            <pin_maps>
311
              <pin_map port_index="0" component_pin="JA10"/> 
312
			</pin_maps>
313
		  </port_map>
314
		  <port_map logical_port="PIN10_O" physical_port="JA10" dir="out"> 
315
            <pin_maps>
316
              <pin_map port_index="0" component_pin="JA10"/> 
317
			</pin_maps>
318
		  </port_map>
319
		  <port_map logical_port="PIN10_T" physical_port="JA10" dir="out"> 
320
            <pin_maps>
321
              <pin_map port_index="0" component_pin="JA10"/> 
322
			</pin_maps>
323
		  </port_map>
324
        </port_maps>
325
      </interface>
326
	  <interface mode="master" name="jb" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jb">
327
        <port_maps>
328
          <port_map logical_port="PIN1_I" physical_port="JB1" dir="in"> 
329
            <pin_maps>
330
              <pin_map port_index="0" component_pin="JB1"/> 
331
			</pin_maps>
332
		  </port_map>
333
		  <port_map logical_port="PIN1_O" physical_port="JB1" dir="out"> 
334
            <pin_maps>
335
              <pin_map port_index="0" component_pin="JB1"/> 
336
			</pin_maps>
337
		  </port_map>
338
		  <port_map logical_port="PIN1_T" physical_port="JB1" dir="out"> 
339
            <pin_maps>
340
              <pin_map port_index="0" component_pin="JB1"/> 
341
			</pin_maps>
342
		  </port_map>
343
		  <port_map logical_port="PIN2_I" physical_port="JB2" dir="in"> 
344
            <pin_maps>
345
              <pin_map port_index="0" component_pin="JB2"/> 
346
			</pin_maps>
347
		  </port_map>
348
		  <port_map logical_port="PIN2_O" physical_port="JB2" dir="out"> 
349
            <pin_maps>
350
              <pin_map port_index="0" component_pin="JB2"/> 
351
			</pin_maps>
352
		  </port_map>
353
		  <port_map logical_port="PIN2_T" physical_port="JB2" dir="out"> 
354
            <pin_maps>
355
              <pin_map port_index="0" component_pin="JB2"/> 
356
			</pin_maps>
357
		  </port_map>
358
		  <port_map logical_port="PIN3_I" physical_port="JB3" dir="in"> 
359
            <pin_maps>
360
              <pin_map port_index="0" component_pin="JB3"/> 
361
			</pin_maps>
362
		  </port_map>
363
		  <port_map logical_port="PIN3_O" physical_port="JB3" dir="out"> 
364
            <pin_maps>
365
              <pin_map port_index="0" component_pin="JB3"/> 
366
			</pin_maps>
367
		  </port_map>
368
		  <port_map logical_port="PIN3_T" physical_port="JB3" dir="out"> 
369
            <pin_maps>
370
              <pin_map port_index="0" component_pin="JB3"/> 
371
			</pin_maps>
372
		  </port_map>
373
		  <port_map logical_port="PIN4_I" physical_port="JB4" dir="in"> 
374
            <pin_maps>
375
              <pin_map port_index="0" component_pin="JB4"/> 
376
			</pin_maps>
377
		  </port_map>
378
		  <port_map logical_port="PIN4_O" physical_port="JB4" dir="out"> 
379
            <pin_maps>
380
              <pin_map port_index="0" component_pin="JB4"/> 
381
			</pin_maps>
382
		  </port_map>
383
		  <port_map logical_port="PIN4_T" physical_port="JB4" dir="out"> 
384
            <pin_maps>
385
              <pin_map port_index="0" component_pin="JB4"/> 
386
			</pin_maps>
387
		  </port_map>
388
		  <port_map logical_port="PIN7_I" physical_port="JB7" dir="in"> 
389
            <pin_maps>
390
              <pin_map port_index="0" component_pin="JB7"/> 
391
			</pin_maps>
392
		  </port_map>
393
		  <port_map logical_port="PIN7_O" physical_port="JB7" dir="out"> 
394
            <pin_maps>
395
              <pin_map port_index="0" component_pin="JB7"/> 
396
			</pin_maps>
397
		  </port_map>
398
		  <port_map logical_port="PIN7_T" physical_port="JB7" dir="out"> 
399
            <pin_maps>
400
              <pin_map port_index="0" component_pin="JB7"/> 
401
			</pin_maps>
402
		  </port_map>
403
		  <port_map logical_port="PIN8_I" physical_port="JB8" dir="in"> 
404
            <pin_maps>
405
              <pin_map port_index="0" component_pin="JB8"/> 
406
			</pin_maps>
407
		  </port_map>
408
		  <port_map logical_port="PIN8_O" physical_port="JB8" dir="out"> 
409
            <pin_maps>
410
              <pin_map port_index="0" component_pin="JB8"/> 
411
			</pin_maps>
412
		  </port_map>
413
		  <port_map logical_port="PIN8_T" physical_port="JB8" dir="out"> 
414
            <pin_maps>
415
              <pin_map port_index="0" component_pin="JB8"/> 
416
			</pin_maps>
417
		  </port_map>
418
		  <port_map logical_port="PIN9_I" physical_port="JB9" dir="in"> 
419
            <pin_maps>
420
              <pin_map port_index="0" component_pin="JB9"/> 
421
			</pin_maps>
422
		  </port_map>
423
		  <port_map logical_port="PIN9_O" physical_port="JB9" dir="out"> 
424
            <pin_maps>
425
              <pin_map port_index="0" component_pin="JB9"/> 
426
			</pin_maps>
427
		  </port_map>
428
		  <port_map logical_port="PIN9_T" physical_port="JB9" dir="out"> 
429
            <pin_maps>
430
              <pin_map port_index="0" component_pin="JB9"/> 
431
			</pin_maps>
432
		  </port_map>
433
		  <port_map logical_port="PIN10_I" physical_port="JB10" dir="in"> 
434
            <pin_maps>
435
              <pin_map port_index="0" component_pin="JB10"/> 
436
			</pin_maps>
437
		  </port_map>
438
		  <port_map logical_port="PIN10_O" physical_port="JB10" dir="out"> 
439
            <pin_maps>
440
              <pin_map port_index="0" component_pin="JB10"/> 
441
			</pin_maps>
442
		  </port_map>
443
		  <port_map logical_port="PIN10_T" physical_port="JB10" dir="out"> 
444
            <pin_maps>
445
              <pin_map port_index="0" component_pin="JB10"/> 
446
			</pin_maps>
447
		  </port_map>
448
        </port_maps>
449
      </interface>
450
	  <interface mode="master" name="jc" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jc">
451
        <port_maps>
452
          <port_map logical_port="PIN1_I" physical_port="JC1" dir="in"> 
453
            <pin_maps>
454
              <pin_map port_index="0" component_pin="JC1"/> 
455
			</pin_maps>
456
		  </port_map>
457
		  <port_map logical_port="PIN1_O" physical_port="JC1" dir="out"> 
458
            <pin_maps>
459
              <pin_map port_index="0" component_pin="JC1"/> 
460
			</pin_maps>
461
		  </port_map>
462
		  <port_map logical_port="PIN1_T" physical_port="JC1" dir="out"> 
463
            <pin_maps>
464
              <pin_map port_index="0" component_pin="JC1"/> 
465
			</pin_maps>
466
		  </port_map>
467
		  <port_map logical_port="PIN2_I" physical_port="JC2" dir="in"> 
468
            <pin_maps>
469
              <pin_map port_index="0" component_pin="JC2"/> 
470
			</pin_maps>
471
		  </port_map>
472
		  <port_map logical_port="PIN2_O" physical_port="JC2" dir="out"> 
473
            <pin_maps>
474
              <pin_map port_index="0" component_pin="JC2"/> 
475
			</pin_maps>
476
		  </port_map>
477
		  <port_map logical_port="PIN2_T" physical_port="JC2" dir="out"> 
478
            <pin_maps>
479
              <pin_map port_index="0" component_pin="JC2"/> 
480
			</pin_maps>
481
		  </port_map>
482
		  <port_map logical_port="PIN3_I" physical_port="JC3" dir="in"> 
483
            <pin_maps>
484
              <pin_map port_index="0" component_pin="JC3"/> 
485
			</pin_maps>
486
		  </port_map>
487
		  <port_map logical_port="PIN3_O" physical_port="JC3" dir="out"> 
488
            <pin_maps>
489
              <pin_map port_index="0" component_pin="JC3"/> 
490
			</pin_maps>
491
		  </port_map>
492
		  <port_map logical_port="PIN3_T" physical_port="JC3" dir="out"> 
493
            <pin_maps>
494
              <pin_map port_index="0" component_pin="JC3"/> 
495
			</pin_maps>
496
		  </port_map>
497
		  <port_map logical_port="PIN4_I" physical_port="JC4" dir="in"> 
498
            <pin_maps>
499
              <pin_map port_index="0" component_pin="JC4"/> 
500
			</pin_maps>
501
		  </port_map>
502
		  <port_map logical_port="PIN4_O" physical_port="JC4" dir="out"> 
503
            <pin_maps>
504
              <pin_map port_index="0" component_pin="JC4"/> 
505
			</pin_maps>
506
		  </port_map>
507
		  <port_map logical_port="PIN4_T" physical_port="JC4" dir="out"> 
508
            <pin_maps>
509
              <pin_map port_index="0" component_pin="JC4"/> 
510
			</pin_maps>
511
		  </port_map>
512
		  <port_map logical_port="PIN7_I" physical_port="JC7" dir="in"> 
513
            <pin_maps>
514
              <pin_map port_index="0" component_pin="JC7"/> 
515
			</pin_maps>
516
		  </port_map>
517
		  <port_map logical_port="PIN7_O" physical_port="JC7" dir="out"> 
518
            <pin_maps>
519
              <pin_map port_index="0" component_pin="JC7"/> 
520
			</pin_maps>
521
		  </port_map>
522
		  <port_map logical_port="PIN7_T" physical_port="JC7" dir="out"> 
523
            <pin_maps>
524
              <pin_map port_index="0" component_pin="JC7"/> 
525
			</pin_maps>
526
		  </port_map>
527
		  <port_map logical_port="PIN8_I" physical_port="JC8" dir="in"> 
528
            <pin_maps>
529
              <pin_map port_index="0" component_pin="JC8"/> 
530
			</pin_maps>
531
		  </port_map>
532
		  <port_map logical_port="PIN8_O" physical_port="JC8" dir="out"> 
533
            <pin_maps>
534
              <pin_map port_index="0" component_pin="JC8"/> 
535
			</pin_maps>
536
		  </port_map>
537
		  <port_map logical_port="PIN8_T" physical_port="JC8" dir="out"> 
538
            <pin_maps>
539
              <pin_map port_index="0" component_pin="JC8"/> 
540
			</pin_maps>
541
		  </port_map>
542
		  <port_map logical_port="PIN9_I" physical_port="JC9" dir="in"> 
543
            <pin_maps>
544
              <pin_map port_index="0" component_pin="JC9"/> 
545
			</pin_maps>
546
		  </port_map>
547
		  <port_map logical_port="PIN9_O" physical_port="JC9" dir="out"> 
548
            <pin_maps>
549
              <pin_map port_index="0" component_pin="JC9"/> 
550
			</pin_maps>
551
		  </port_map>
552
		  <port_map logical_port="PIN9_T" physical_port="JC9" dir="out"> 
553
            <pin_maps>
554
              <pin_map port_index="0" component_pin="JC9"/> 
555
			</pin_maps>
556
		  </port_map>
557
		  <port_map logical_port="PIN10_I" physical_port="JC10" dir="in"> 
558
            <pin_maps>
559
              <pin_map port_index="0" component_pin="JC10"/> 
560
			</pin_maps>
561
		  </port_map>
562
		  <port_map logical_port="PIN10_O" physical_port="JC10" dir="out"> 
563
            <pin_maps>
564
              <pin_map port_index="0" component_pin="JC10"/> 
565
			</pin_maps>
566
		  </port_map>
567
		  <port_map logical_port="PIN10_T" physical_port="JC10" dir="out"> 
568
            <pin_maps>
569
              <pin_map port_index="0" component_pin="JC10"/> 
570
			</pin_maps>
571
		  </port_map>
572
        </port_maps>
573
      </interface>
574
	  <interface mode="master" name="jd" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jd">
575
        <port_maps>
576
          <port_map logical_port="PIN1_I" physical_port="JD1" dir="in"> 
577
            <pin_maps>
578
              <pin_map port_index="0" component_pin="JD1"/> 
579
			</pin_maps>
580
		  </port_map>
581
		  <port_map logical_port="PIN1_O" physical_port="JD1" dir="out"> 
582
            <pin_maps>
583
              <pin_map port_index="0" component_pin="JD1"/> 
584
			</pin_maps>
585
		  </port_map>
586
		  <port_map logical_port="PIN1_T" physical_port="JD1" dir="out"> 
587
            <pin_maps>
588
              <pin_map port_index="0" component_pin="JD1"/> 
589
			</pin_maps>
590
		  </port_map>
591
		  <port_map logical_port="PIN2_I" physical_port="JD2" dir="in"> 
592
            <pin_maps>
593
              <pin_map port_index="0" component_pin="JD2"/> 
594
			</pin_maps>
595
		  </port_map>
596
		  <port_map logical_port="PIN2_O" physical_port="JD2" dir="out"> 
597
            <pin_maps>
598
              <pin_map port_index="0" component_pin="JD2"/> 
599
			</pin_maps>
600
		  </port_map>
601
		  <port_map logical_port="PIN2_T" physical_port="JD2" dir="out"> 
602
            <pin_maps>
603
              <pin_map port_index="0" component_pin="JD2"/> 
604
			</pin_maps>
605
		  </port_map>
606
		  <port_map logical_port="PIN3_I" physical_port="JD3" dir="in"> 
607
            <pin_maps>
608
              <pin_map port_index="0" component_pin="JD3"/> 
609
			</pin_maps>
610
		  </port_map>
611
		  <port_map logical_port="PIN3_O" physical_port="JD3" dir="out"> 
612
            <pin_maps>
613
              <pin_map port_index="0" component_pin="JD3"/> 
614
			</pin_maps>
615
		  </port_map>
616
		  <port_map logical_port="PIN3_T" physical_port="JD3" dir="out"> 
617
            <pin_maps>
618
              <pin_map port_index="0" component_pin="JD3"/> 
619
			</pin_maps>
620
		  </port_map>
621
		  <port_map logical_port="PIN4_I" physical_port="JD4" dir="in"> 
622
            <pin_maps>
623
              <pin_map port_index="0" component_pin="JD4"/> 
624
			</pin_maps>
625
		  </port_map>
626
		  <port_map logical_port="PIN4_O" physical_port="JD4" dir="out"> 
627
            <pin_maps>
628
              <pin_map port_index="0" component_pin="JD4"/> 
629
			</pin_maps>
630
		  </port_map>
631
		  <port_map logical_port="PIN4_T" physical_port="JD4" dir="out"> 
632
            <pin_maps>
633
              <pin_map port_index="0" component_pin="JD4"/> 
634
			</pin_maps>
635
		  </port_map>
636
		  <port_map logical_port="PIN7_I" physical_port="JD7" dir="in"> 
637
            <pin_maps>
638
              <pin_map port_index="0" component_pin="JD7"/> 
639
			</pin_maps>
640
		  </port_map>
641
		  <port_map logical_port="PIN7_O" physical_port="JD7" dir="out"> 
642
            <pin_maps>
643
              <pin_map port_index="0" component_pin="JD7"/> 
644
			</pin_maps>
645
		  </port_map>
646
		  <port_map logical_port="PIN7_T" physical_port="JD7" dir="out"> 
647
            <pin_maps>
648
              <pin_map port_index="0" component_pin="JD7"/> 
649
			</pin_maps>
650
		  </port_map>
651
		  <port_map logical_port="PIN8_I" physical_port="JD8" dir="in"> 
652
            <pin_maps>
653
              <pin_map port_index="0" component_pin="JD8"/> 
654
			</pin_maps>
655
		  </port_map>
656
		  <port_map logical_port="PIN8_O" physical_port="JD8" dir="out"> 
657
            <pin_maps>
658
              <pin_map port_index="0" component_pin="JD8"/> 
659
			</pin_maps>
660
		  </port_map>
661
		  <port_map logical_port="PIN8_T" physical_port="JD8" dir="out"> 
662
            <pin_maps>
663
              <pin_map port_index="0" component_pin="JD8"/> 
664
			</pin_maps>
665
		  </port_map>
666
		  <port_map logical_port="PIN9_I" physical_port="JD9" dir="in"> 
667
            <pin_maps>
668
              <pin_map port_index="0" component_pin="JD9"/> 
669
			</pin_maps>
670
		  </port_map>
671
		  <port_map logical_port="PIN9_O" physical_port="JD9" dir="out"> 
672
            <pin_maps>
673
              <pin_map port_index="0" component_pin="JD9"/> 
674
			</pin_maps>
675
		  </port_map>
676
		  <port_map logical_port="PIN9_T" physical_port="JD9" dir="out"> 
677
            <pin_maps>
678
              <pin_map port_index="0" component_pin="JD9"/> 
679
			</pin_maps>
680
		  </port_map>
681
		  <port_map logical_port="PIN10_I" physical_port="JD10" dir="in"> 
682
            <pin_maps>
683
              <pin_map port_index="0" component_pin="JD10"/> 
684
			</pin_maps>
685
		  </port_map>
686
		  <port_map logical_port="PIN10_O" physical_port="JD10" dir="out"> 
687
            <pin_maps>
688
              <pin_map port_index="0" component_pin="JD10"/> 
689
			</pin_maps>
690
		  </port_map>
691
		  <port_map logical_port="PIN10_T" physical_port="JD10" dir="out"> 
692
            <pin_maps>
693
              <pin_map port_index="0" component_pin="JD10"/> 
694
			</pin_maps>
695
		  </port_map>
696
        </port_maps>
697
      </interface>
698
	  <interface mode="master" name="je" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="je">
699
        <port_maps>
700
          <port_map logical_port="PIN1_I" physical_port="JE1" dir="in"> 
701
            <pin_maps>
702
              <pin_map port_index="0" component_pin="JE1"/> 
703
			</pin_maps>
704
		  </port_map>
705
		  <port_map logical_port="PIN1_O" physical_port="JE1" dir="out"> 
706
            <pin_maps>
707
              <pin_map port_index="0" component_pin="JE1"/> 
708
			</pin_maps>
709
		  </port_map>
710
		  <port_map logical_port="PIN1_T" physical_port="JE1" dir="out"> 
711
            <pin_maps>
712
              <pin_map port_index="0" component_pin="JE1"/> 
713
			</pin_maps>
714
		  </port_map>
715
		  <port_map logical_port="PIN2_I" physical_port="JE2" dir="in"> 
716
            <pin_maps>
717
              <pin_map port_index="0" component_pin="JE2"/> 
718
			</pin_maps>
719
		  </port_map>
720
		  <port_map logical_port="PIN2_O" physical_port="JE2" dir="out"> 
721
            <pin_maps>
722
              <pin_map port_index="0" component_pin="JE2"/> 
723
			</pin_maps>
724
		  </port_map>
725
		  <port_map logical_port="PIN2_T" physical_port="JE2" dir="out"> 
726
            <pin_maps>
727
              <pin_map port_index="0" component_pin="JE2"/> 
728
			</pin_maps>
729
		  </port_map>
730
		  <port_map logical_port="PIN3_I" physical_port="JE3" dir="in"> 
731
            <pin_maps>
732
              <pin_map port_index="0" component_pin="JE3"/> 
733
			</pin_maps>
734
		  </port_map>
735
		  <port_map logical_port="PIN3_O" physical_port="JE3" dir="out"> 
736
            <pin_maps>
737
              <pin_map port_index="0" component_pin="JE3"/> 
738
			</pin_maps>
739
		  </port_map>
740
		  <port_map logical_port="PIN3_T" physical_port="JE3" dir="out"> 
741
            <pin_maps>
742
              <pin_map port_index="0" component_pin="JE3"/> 
743
			</pin_maps>
744
		  </port_map>
745
		  <port_map logical_port="PIN4_I" physical_port="JE4" dir="in"> 
746
            <pin_maps>
747
              <pin_map port_index="0" component_pin="JE4"/> 
748
			</pin_maps>
749
		  </port_map>
750
		  <port_map logical_port="PIN4_O" physical_port="JE4" dir="out"> 
751
            <pin_maps>
752
              <pin_map port_index="0" component_pin="JE4"/> 
753
			</pin_maps>
754
		  </port_map>
755
		  <port_map logical_port="PIN4_T" physical_port="JE4" dir="out"> 
756
            <pin_maps>
757
              <pin_map port_index="0" component_pin="JE4"/> 
758
			</pin_maps>
759
		  </port_map>
760
		  <port_map logical_port="PIN7_I" physical_port="JE7" dir="in"> 
761
            <pin_maps>
762
              <pin_map port_index="0" component_pin="JE7"/> 
763
			</pin_maps>
764
		  </port_map>
765
		  <port_map logical_port="PIN7_O" physical_port="JE7" dir="out"> 
766
            <pin_maps>
767
              <pin_map port_index="0" component_pin="JE7"/> 
768
			</pin_maps>
769
		  </port_map>
770
		  <port_map logical_port="PIN7_T" physical_port="JE7" dir="out"> 
771
            <pin_maps>
772
              <pin_map port_index="0" component_pin="JE7"/> 
773
			</pin_maps>
774
		  </port_map>
775
		  <port_map logical_port="PIN8_I" physical_port="JE8" dir="in"> 
776
            <pin_maps>
777
              <pin_map port_index="0" component_pin="JE8"/> 
778
			</pin_maps>
779
		  </port_map>
780
		  <port_map logical_port="PIN8_O" physical_port="JE8" dir="out"> 
781
            <pin_maps>
782
              <pin_map port_index="0" component_pin="JE8"/> 
783
			</pin_maps>
784
		  </port_map>
785
		  <port_map logical_port="PIN8_T" physical_port="JE8" dir="out"> 
786
            <pin_maps>
787
              <pin_map port_index="0" component_pin="JE8"/> 
788
			</pin_maps>
789
		  </port_map>
790
		  <port_map logical_port="PIN9_I" physical_port="JE9" dir="in"> 
791
            <pin_maps>
792
              <pin_map port_index="0" component_pin="JE9"/> 
793
			</pin_maps>
794
		  </port_map>
795
		  <port_map logical_port="PIN9_O" physical_port="JE9" dir="out"> 
796
            <pin_maps>
797
              <pin_map port_index="0" component_pin="JE9"/> 
798
			</pin_maps>
799
		  </port_map>
800
		  <port_map logical_port="PIN9_T" physical_port="JE9" dir="out"> 
801
            <pin_maps>
802
              <pin_map port_index="0" component_pin="JE9"/> 
803
			</pin_maps>
804
		  </port_map>
805
		  <port_map logical_port="PIN10_I" physical_port="JE10" dir="in"> 
806
            <pin_maps>
807
              <pin_map port_index="0" component_pin="JE10"/> 
808
			</pin_maps>
809
		  </port_map>
810
		  <port_map logical_port="PIN10_O" physical_port="JE10" dir="out"> 
811
            <pin_maps>
812
              <pin_map port_index="0" component_pin="JE10"/> 
813
			</pin_maps>
814
		  </port_map>
815
		  <port_map logical_port="PIN10_T" physical_port="JE10" dir="out"> 
816
            <pin_maps>
817
              <pin_map port_index="0" component_pin="JE10"/> 
818
			</pin_maps>
819
		  </port_map>
820
        </port_maps>
821
      </interface>
822
	  <interface mode="master" name="rgb_led" type="xilinx.com:interface:gpio_rtl:1.0" of_component="rgb_led" preset_proc="rgb_led_preset">
823
        <description>2 RGB LEDs</description>
824
		<preferred_ips>
825
			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
826
		</preferred_ips>
827
		<port_maps>
828
          <port_map logical_port="TRI_O" physical_port="rgb_led_tri_o" dir="out" left="5" right="0"> 
829
            <pin_maps>
830
              <pin_map port_index="0" component_pin="rgb_led_tri_o_0"/> 
831
              <pin_map port_index="1" component_pin="rgb_led_tri_o_1"/> 
832
              <pin_map port_index="2" component_pin="rgb_led_tri_o_2"/> 
833
              <pin_map port_index="3" component_pin="rgb_led_tri_o_3"/> 
834
              <pin_map port_index="4" component_pin="rgb_led_tri_o_4"/> 
835
              <pin_map port_index="5" component_pin="rgb_led_tri_o_5"/> 
836
            </pin_maps>
837
          </port_map>
838
        </port_maps>
839
      </interface>
840
    </interfaces>
841
  </component>
842
  
843
  <component name="btns_4bits" display_name="4 Buttons" type="chip" sub_type="push_button" major_group="GPIO">
844
	<description>Buttons 3 to 0</description>
845
  </component>
846
  <component name="ja" display_name="Connector JA" type="chip" sub_type="chip" major_group="Pmod">
847
	<description>Pmod Connector JA</description>
848
  </component>
849
  <component name="jb" display_name="Connector JB" type="chip" sub_type="chip" major_group="Pmod">
850
	<description>Pmod Connector JB</description>
851
  </component>
852
  <component name="jc" display_name="Connector JC" type="chip" sub_type="chip" major_group="Pmod">
853
	<description>Pmod Connector JC</description>
854
  </component>
855
  <component name="jd" display_name="Connector JD" type="chip" sub_type="chip" major_group="Pmod">
856
	<description>Pmod Connector JD</description>
857
  </component>
858
  <component name="je" display_name="Connector JE" type="chip" sub_type="chip" major_group="Pmod">
859
	<description>Pmod Connector JE</description>
860
  </component>
861
  <component name="leds_4bits" display_name="4 LEDs" type="chip" sub_type="led" major_group="GPIO">
862
	<description>LEDs 3 to 0</description>
863
  </component>
864
  <component name="ps7_fixedio" display_name="ps7_fixedio" type="chip" sub_type="fixed_io" major_group=""/>
865
  <component name="sws_4bits" display_name="4 Switches" type="chip" sub_type="switch" major_group="GPIO">
866
	<description>DIP Switches 3 to 0</description>
867
  </component>
868
  <component name="sys_clock" display_name="System Clock" type="chip" sub_type="system_clock" major_group="Clocks">
869
	<description>3.3V Single-Ended 50 MHz oscillator used as system clock on the board</description>
870
  </component>
871
  <component name="rgb_led" display_name="2 RGB LEDS" type="chip" sub_type="led" major_group="GPIO">
872
	<description>RGB leds 5 to 0 (3 per LED, Ordered "RGBRGB")</description>
873
  </component>  
874
  
875
  <component name="hdmi_in" display_name="HDMI In" type="chip" sub_type="fixed_io" major_group="HDMI">
876
	<description>HDMI input (Requires Digilent's TMDS interface)</description>
877
	<component_modes>
878
        <component_mode name="HDMI_IN" display_name="HDMI In">
879
		  <interfaces>
880
            <interface name="hdmi_in" order="0"/>
881
            <interface name="hdmi_in_ddc" order="1"/>
882
          </interfaces>
883
		</component_mode>
884
	 </component_modes>
885
  </component>
886
  <component name="hdmi_in_hpd_led" display_name="HDMI In HPD" type="chip" sub_type="led" major_group="HDMI">
887
	<description>HDMI in HPD (Connected to LD8)</description>
888
  </component>
889
  <component name="hdmi_out" display_name="HDMI out" type="chip" sub_type="fixed_io" major_group="HDMI">
890
	<description>HDMI Out (Requires Digilent's TMDS interface)</description>
891
  </component>
892
  <component name="hdmi_out_hpd_led" display_name="HDMI out HPD" type="chip" sub_type="led" major_group="HDMI">
893
	<description>HDMI out HPD</description>
894
  </component>
895

    
896
  
897
  
898
  
899
</components>
900
<jtag_chains>
901
  <jtag_chain name="chain1">
902
    <position name="0" component="part0"/>
903
  </jtag_chain>
904
</jtag_chains>
905
<connections>
906
  <connection name="part0_btns_4bits" component1="part0" component2="btns_4bits">
907
    <connection_map name="part0_btns_4bits_1" c1_st_index="0" c1_end_index="3" c2_st_index="0" c2_end_index="3"/>
908
  </connection>
909
  <connection name="part0_leds_4bits" component1="part0" component2="leds_4bits">
910
    <connection_map name="part0_leds_4bits_1" c1_st_index="4" c1_end_index="7" c2_st_index="0" c2_end_index="3"/>
911
  </connection>
912
  <connection name="part0_sws_4bits" component1="part0" component2="sws_4bits">
913
    <connection_map name="part0_sws_4bits_1" c1_st_index="8" c1_end_index="11" c2_st_index="0" c2_end_index="3"/>
914
  </connection>
915
  <connection name="part0_sys_clock" component1="part0" component2="sys_clock">
916
    <connection_map name="part0_sys_clock_1" c1_st_index="12" c1_end_index="12" c2_st_index="0" c2_end_index="0"/>
917
  </connection>
918
  
919
   
920
  <connection name="part0_hdmi_in" component1="part0" component2="hdmi_in">
921
    <connection_map name="part0_hdmi_in_1" c1_st_index="14" c1_end_index="21" c2_st_index="0" c2_end_index="7"/>
922
	
923
	<connection_map name="part0_hdmi_in_ddc" c1_st_index="31" c1_end_index="32" c2_st_index="0" c2_end_index="1"/>
924
  </connection>
925
  
926
  <connection name="part0_hdmi_in_hpd_led" component1="part0" component2="hdmi_in_hpd_led">
927
    <connection_map name="part0_hdmi_in_hpd_led_1" c1_st_index="13" c1_end_index="13" c2_st_index="0" c2_end_index="0"/>
928
  </connection>
929
  
930
  <connection name="part0_hdmi_out" component1="part0" component2="hdmi_out">
931
    <connection_map name="part0_hdmi_out_1" c1_st_index="23" c1_end_index="30" c2_st_index="0" c2_end_index="7"/>
932
  </connection>
933
  
934
  <connection name="part0_hdmi_out_hpd_led" component1="part0" component2="hdmi_out_hpd_led">
935
    <connection_map name="part0_hdmi_out_hpd_led_1" c1_st_index="22" c1_end_index="22" c2_st_index="0" c2_end_index="0"/>
936
  </connection>
937
   
938
  
939
  <connection name="part0_ja" component1="part0" component2="ja">
940
    <connection_map name="part0_ja_1" c1_st_index="39" c1_end_index="46" c2_st_index="0" c2_end_index="7"/>
941
  </connection>
942
  <connection name="part0_jb" component1="part0" component2="jb">
943
    <connection_map name="part0_jb_1" c1_st_index="47" c1_end_index="54" c2_st_index="0" c2_end_index="7"/>
944
  </connection>
945
  <connection name="part0_jc" component1="part0" component2="jc">
946
    <connection_map name="part0_jc_1" c1_st_index="55" c1_end_index="62" c2_st_index="0" c2_end_index="7"/>
947
  </connection>
948
  <connection name="part0_jd" component1="part0" component2="jd">
949
    <connection_map name="part0_jd_1" c1_st_index="63" c1_end_index="70" c2_st_index="0" c2_end_index="7"/>
950
  </connection>
951
  <connection name="part0_je" component1="part0" component2="je">
952
    <connection_map name="part0_je_1" c1_st_index="71" c1_end_index="78" c2_st_index="0" c2_end_index="7"/>
953
  </connection>
954
  <connection name="part0_rgb_led" component1="part0" component2="rgb_led">
955
    <connection_map name="part0_rgb_led_1" c1_st_index="33" c1_end_index="38" c2_st_index="0" c2_end_index="5"/>
956
  </connection>  
957
</connections>
958
</board>
(1-1/2)