HELPDESK_WJ (Waijung)

Hi Johan,

Thank you for the feedback.

I see one particular message mentioning that the constraint file is not available. Did you go through the process of downloading and copying the constraint files/board files to your vivado installation?
We have mentioned this under step 12 of the prerequisite section of the user guide.

Step 12: Once the installation is finish successfully. Install Digilent's Board Files to add Zybo Z7-20 board to the Vivado design suite

https://digilent.com/reference/programmable-logic/guides/installing-vivado-and-vitis#install_digilent_s_board_files

If this is not the first tcl file from a demo you have attempted to run, then it is likely not a board file issue.

Please confirm that the board files are available in the location expected by vivado before we proceed further.

Best Regards,
Shawn

Hi Johan,

It is much more likely that the board part file versions are not compatible.

issued the command: get_board_parts zybo
result: digilentinc.com:zybo-z7-10:part0:1.1 digilentinc.com:zybo-z7-20:part0:1.1 digilentinc.com:zybo:part0:1.0 digilentinc.com:zybo:part0:2.0

It looks like you have zybo-z7-20:part0:1.1 installed. During the implementation and testing of the blockset only version 1.0 of these files were available.

There are 2 possible solutions for this.

1) Go to line 135 of the zybo7z20_adc_demo.tcl file and change the version to 1.1. (we have not tested this extensively. So we recommend the second solution instead. Plus you would have to edit every tcl script for other demos this way if you intend to run them.)
2) download and install the older part files (no need to edit the tcl file for this solution)

Please let us know your findings.

Best Regards,
Shawn

Hello Shawn,

Thanks for helping with this issue. I installed the older board files but now I ran into other errors. Can you have a look into it, please?

This is my directory:
pwd
C:/AimaginProjects/Z7000/adc_demo/hardware_design/vivado_tcl

This is what resides in it:
ls
adc_demo
readme.txt
xdc
zybo7z20_adc_demo.tcl

These are the zybo boards in Vivado:
get_board_parts zy
digilentinc.com:zybo-z7-10:part0:1.1 digilentinc.com:zybo-z7-20:part0:1.0 digilentinc.com:zybo:part0:1.0 digilentinc.com:zybo:part0:2.0

1. proc checkRequiredFiles { origin_dir} {
2. set status true
3. set files [list \
4. "xdc/Zybo-Z7-Master.xdc" \
5. ]
6. foreach ifile $files {
7. if { ![file isfile $ifile] } {
8. puts " Could not find local file $ifile "
9. set status false
10. }
11. }
13. return $status
14. }
15. set origin_dir "."
16. if { [info exists ::origin_dir_loc] } {
17. set origin_dir $::origin_dir_loc
18. }
19. set xil_proj_name "adc_demo"
20. if { [info exists ::user_project_name] } {
21. set xil_proj_name $::user_project_name
22. }
23. variable script_file
24. set script_file "zybo7z20_adc_demo.tcl"
25. proc print_help {} {
26. variable script_file
27. puts "\nDescription:"
28. puts "Recreate a Vivado project from this script. The created project will be"
29. puts "functionally equivalent to the original project for which this script was"
30. puts "generated. The script contains commands for creating a project, filesets,"
31. puts "runs, adding/importing sources and setting properties on various objects.\n"
32. puts "Syntax:"
33. puts "$script_file"
34. puts "$script_file -tclargs \[--origin_dir <path>\]"
35. puts "$script_file -tclargs \[--project_name <name>\]"
36. puts "$script_file -tclargs \[--help\]\n"
37. puts "Usage:"
38. puts "Name Description"
39. puts "-------------------------------------------------------------------------"
40. puts "\[--origin_dir <path>\] Determine source file paths wrt this path. Default"
41. puts " origin_dir path value is \".\", otherwise, the value"
42. puts " that was set with the \"-paths_relative_to\" switch"
43. puts " when this script was generated.\n"
44. puts "\[--project_name <name>\] Create project with the specified name. Default"
45. puts " name is the name of the project from where this"
46. puts " script was generated.\n"
47. puts "\[--help\] Print help information for this script"
48. puts "-------------------------------------------------------------------------\n"
49. exit 0
50. }
51. if { $::argc > 0 } {
52. for {set i 0} {$i < $::argc} {incr i} {
53. set option [string trim [lindex $::argv $i]]
54. switch regexp - $option {
55. "--origin_dir" { incr i; set origin_dir [lindex $::argv $i] }
56. "--project_name" { incr i; set xil_proj_name [lindex $::argv $i] }
57. "--help" { print_help }
58. default {
59. if { [regexp {^-} $option] } {
60. puts "ERROR: Unknown option '$option' specified, please type '$script_file -tclargs --help' for usage info.\n"
61. return 1
62. }
63. }
64. }
65. }
66. }
67. set orig_proj_dir "[file normalize "$origin_dir/adc_demo"]"
68. set validate_required 0
69. if { $validate_required } {
70. if { [checkRequiredFiles $origin_dir] } {
71. puts "Tcl file $script_file is valid. All files required for project creation is accesable. "
72. } else {
73. puts "Tcl file $script_file is not valid. Not all files required for project creation is accesable. "
74. return
75. }
76. }
77. create_project ${_xil_proj_name_} ./${_xil_proj_name_} -part xc7z020clg400-1
    INFO: [IP_Flow 19-234] Refreshing IP repositories
    INFO: [IP_Flow 19-1704] No user IP repositories specified
    INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2020.2/data/ip'.
78. set proj_dir [get_property directory [current_project]]
79. set obj [current_project]
80. set_property -name "board_part" -value "digilentinc.com:zybo-z7-20:part0:1.0" -objects $obj
81. set_property -name "default_lib" -value "xil_defaultlib" -objects $obj
82. set_property -name "enable_vhdl_2008" -value "1" -objects $obj
83. set_property -name "ip_cache_permissions" -value "read write" -objects $obj
84. set_property -name "ip_output_repo" -value "$proj_dir/${_xil_proj_name_}.cache/ip" -objects $obj
85. set_property -name "mem.enable_memory_map_generation" -value "1" -objects $obj
86. set_property -name "platform.board_id" -value "zybo-z7-20" -objects $obj
87. set_property -name "sim.central_dir" -value "$proj_dir/${_xil_proj_name_}.ip_user_files" -objects $obj
88. set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj
89. set_property -name "simulator_language" -value "Mixed" -objects $obj
90. set_property -name "xpm_libraries" -value "XPM_CDC XPM_MEMORY" -objects $obj
91. if {[string equal [get_filesets -quiet sources_1] ""]} {
92. create_fileset -srcset sources_1
93. }
94. set obj [get_filesets sources_1]
95. set obj [get_filesets sources_1]
96. set_property -name "top" -value "design_1_wrapper" -objects $obj
97. if {[string equal [get_filesets -quiet constrs_1] ""]} {
98. create_fileset -constrset constrs_1
99. }
100. set obj [get_filesets constrs_1]
101. set file "[file normalize "xdc/Zybo-Z7-Master.xdc"]"
102. set file_imported [import_files -fileset constrs_1 [list $file]]
103. set file "xdc/Zybo-Z7-Master.xdc"
104. set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]]
105. set_property -name "file_type" -value "XDC" -objects $file_obj
106. set obj [get_filesets constrs_1]
     WARNING: [Vivado 12-818] No files matched 'xdc/Zybo-Z7-Master.xdc'
107. set_property -name "target_constrs_file" -value "[get_files xdc/Zybo-Z7-Master.xdc]" -objects $obj
     WARNING: [Vivado 12-818] No files matched 'xdc/Zybo-Z7-Master.xdc'
108. set_property -name "target_ucf" -value "[get_files xdc/Zybo-Z7-Master.xdc]" -objects $obj
109. if {[string equal [get_filesets -quiet sim_1] ""]} {
110. create_fileset -simset sim_1
111. }
112. set obj [get_filesets sim_1]
113. set obj [get_filesets sim_1]
114. set_property -name "hbs.configure_design_for_hier_access" -value "1" -objects $obj
115. set_property -name "top" -value "design_1_wrapper" -objects $obj
116. set_property -name "top_lib" -value "xil_defaultlib" -objects $obj
117. set obj [get_filesets utils_1]
118. set obj [get_filesets utils_1]
119. proc cr_bd_design_1 { parentCell } {
121. # CHANGE DESIGN NAME HERE
122. set design_name design_1
124. common::send_gid_msg -ssname BD::TCL -id 2010 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..."
126. create_bd_design $design_name
128. set bCheckIPsPassed 1
129. ##################################################################
130. # CHECK IPs
131. ##################################################################
132. set bCheckIPs 1
133. if { $bCheckIPs == 1 } {
134. set list_check_ips "\
135. xilinx.com:ip:processing_system7:5.5\
136. xilinx.com:ip:proc_sys_reset:5.0\
137. xilinx.com:ip:xadc_wiz:3.3\
138. "
140. set list_ips_missing ""
141. common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
143. foreach ip_vlnv $list_check_ips {
144. set ip_obj [get_ipdefs -all $ip_vlnv]
145. if { $ip_obj eq "" } {
146. lappend list_ips_missing $ip_vlnv
147. }
148. }
150. if { $list_ips_missing ne "" } {
151. catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP to the project." }
152. set bCheckIPsPassed 0
153. }
155. }
157. if { $bCheckIPsPassed != 1 } {
158. common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above."
159. return 3
160. }
162. variable script_folder
164. if { $parentCell eq "" } {
165. set parentCell [get_bd_cells /]
166. }
168. # Get object for parentCell
169. set parentObj [get_bd_cells $parentCell]
170. if { $parentObj == "" } {
171. catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
172. return
173. }
175. # Make sure parentObj is hier blk
176. set parentType [get_property TYPE $parentObj]
177. if { $parentType ne "hier" } {
178. catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
179. return
180. }
182. # Save current instance; Restore later
183. set oldCurInst [current_bd_instance .]
185. # Set parent object as current
186. current_bd_instance $parentObj
189. # Create interface ports
190. set DDR [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR ]
192. set FIXED_IO [ create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 FIXED_IO ]
194. set Vaux6 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vaux6 ]
196. set Vaux7 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vaux7 ]
198. set Vaux14 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vaux14 ]
200. set Vaux15 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vaux15 ]
203. # Create ports
205. # Create instance: processing_system7_0, and set properties
206. set processing_system7_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0 ]
207. set_property -dict [ list \
208. CONFIG.PCW_ACT_APU_PERIPHERAL_FREQMHZ {666.666687} \
209. CONFIG.PCW_ACT_CAN_PERIPHERAL_FREQMHZ {10.000000} \
210. CONFIG.PCW_ACT_DCI_PERIPHERAL_FREQMHZ {10.158730} \
211. CONFIG.PCW_ACT_ENET0_PERIPHERAL_FREQMHZ {125.000000} \
212. CONFIG.PCW_ACT_ENET1_PERIPHERAL_FREQMHZ {10.000000} \
213. CONFIG.PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ {50.000000} \
214. CONFIG.PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ {10.000000} \
215. CONFIG.PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ {10.000000} \
216. CONFIG.PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ {10.000000} \
217. CONFIG.PCW_ACT_PCAP_PERIPHERAL_FREQMHZ {200.000000} \
218. CONFIG.PCW_ACT_QSPI_PERIPHERAL_FREQMHZ {200.000000} \
219. CONFIG.PCW_ACT_SDIO_PERIPHERAL_FREQMHZ {50.000000} \
220. CONFIG.PCW_ACT_SMC_PERIPHERAL_FREQMHZ {10.000000} \
221. CONFIG.PCW_ACT_SPI_PERIPHERAL_FREQMHZ {10.000000} \
222. CONFIG.PCW_ACT_TPIU_PERIPHERAL_FREQMHZ {200.000000} \
223. CONFIG.PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ {111.111115} \
224. CONFIG.PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ {111.111115} \
225. CONFIG.PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ {111.111115} \
226. CONFIG.PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ {111.111115} \
227. CONFIG.PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ {111.111115} \
228. CONFIG.PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ {111.111115} \
229. CONFIG.PCW_ACT_UART_PERIPHERAL_FREQMHZ {100.000000} \
230. CONFIG.PCW_ACT_WDT_PERIPHERAL_FREQMHZ {111.111115} \
231. CONFIG.PCW_APU_CLK_RATIO_ENABLE {6:2:1} \
232. CONFIG.PCW_APU_PERIPHERAL_FREQMHZ {667} \
233. CONFIG.PCW_ARMPLL_CTRL_FBDIV {40} \
234. CONFIG.PCW_CAN_PERIPHERAL_DIVISOR0 {1} \
235. CONFIG.PCW_CAN_PERIPHERAL_DIVISOR1 {1} \
236. CONFIG.PCW_CLK0_FREQ {50000000} \
237. CONFIG.PCW_CLK1_FREQ {10000000} \
238. CONFIG.PCW_CLK2_FREQ {10000000} \
239. CONFIG.PCW_CLK3_FREQ {10000000} \
240. CONFIG.PCW_CPU_CPU_6X4X_MAX_RANGE {667} \
241. CONFIG.PCW_CPU_CPU_PLL_FREQMHZ {1333.333} \
242. CONFIG.PCW_CPU_PERIPHERAL_CLKSRC {ARM PLL} \
243. CONFIG.PCW_CPU_PERIPHERAL_DIVISOR0 {2} \
244. CONFIG.PCW_CRYSTAL_PERIPHERAL_FREQMHZ {33.333333} \
245. CONFIG.PCW_DCI_PERIPHERAL_CLKSRC {DDR PLL} \
246. CONFIG.PCW_DCI_PERIPHERAL_DIVISOR0 {15} \
247. CONFIG.PCW_DCI_PERIPHERAL_DIVISOR1 {7} \
248. CONFIG.PCW_DCI_PERIPHERAL_FREQMHZ {10.159} \
249. CONFIG.PCW_DDRPLL_CTRL_FBDIV {32} \
250. CONFIG.PCW_DDR_DDR_PLL_FREQMHZ {1066.667} \
251. CONFIG.PCW_DDR_HPRLPR_QUEUE_PARTITION {HPR/LPR} \
252. CONFIG.PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL {15} \
253. CONFIG.PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL {2} \
254. CONFIG.PCW_DDR_PERIPHERAL_CLKSRC {DDR PLL} \
255. CONFIG.PCW_DDR_PERIPHERAL_DIVISOR0 {2} \
256. CONFIG.PCW_DDR_PORT0_HPR_ENABLE {0} \
257. CONFIG.PCW_DDR_PORT1_HPR_ENABLE {0} \
258. CONFIG.PCW_DDR_PORT2_HPR_ENABLE {0} \
259. CONFIG.PCW_DDR_PORT3_HPR_ENABLE {0} \
260. CONFIG.PCW_DDR_RAM_HIGHADDR {0x3FFFFFFF} \
261. CONFIG.PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL {2} \
262. CONFIG.PCW_ENET0_ENET0_IO {MIO 16 .. 27} \
263. CONFIG.PCW_ENET0_GRP_MDIO_ENABLE {1} \
264. CONFIG.PCW_ENET0_GRP_MDIO_IO {MIO 52 .. 53} \
265. CONFIG.PCW_ENET0_PERIPHERAL_CLKSRC {IO PLL} \
266. CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR0 {8} \
267. CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR1 {1} \
268. CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {1} \
269. CONFIG.PCW_ENET0_PERIPHERAL_FREQMHZ {1000 Mbps} \
270. CONFIG.PCW_ENET0_RESET_ENABLE {0} \
271. CONFIG.PCW_ENET1_GRP_MDIO_ENABLE {0} \
272. CONFIG.PCW_ENET1_PERIPHERAL_CLKSRC {IO PLL} \
273. CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR0 {1} \
274. CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR1 {1} \
275. CONFIG.PCW_ENET1_PERIPHERAL_ENABLE {0} \
276. CONFIG.PCW_ENET1_PERIPHERAL_FREQMHZ {1000 Mbps} \
277. CONFIG.PCW_ENET1_RESET_ENABLE {0} \
278. CONFIG.PCW_ENET_RESET_ENABLE {1} \
279. CONFIG.PCW_ENET_RESET_POLARITY {Active Low} \
280. CONFIG.PCW_ENET_RESET_SELECT {Share reset pin} \
281. CONFIG.PCW_EN_4K_TIMER {0} \
282. CONFIG.PCW_EN_ENET0 {1} \
283. CONFIG.PCW_EN_GPIO {1} \
284. CONFIG.PCW_EN_QSPI {1} \
285. CONFIG.PCW_EN_SDIO0 {1} \
286. CONFIG.PCW_EN_UART1 {1} \
287. CONFIG.PCW_EN_USB0 {0} \
288. CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR0 {5} \
289. CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR1 {4} \
290. CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR0 {1} \
291. CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR1 {1} \
292. CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR0 {1} \
293. CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR1 {1} \
294. CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR0 {1} \
295. CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR1 {1} \
296. CONFIG.PCW_FPGA_FCLK0_ENABLE {1} \
297. CONFIG.PCW_FPGA_FCLK1_ENABLE {0} \
298. CONFIG.PCW_FPGA_FCLK2_ENABLE {0} \
299. CONFIG.PCW_FPGA_FCLK3_ENABLE {0} \
300. CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1} \
301. CONFIG.PCW_GPIO_MIO_GPIO_IO {MIO} \
302. CONFIG.PCW_GPIO_PERIPHERAL_ENABLE {0} \
303. CONFIG.PCW_I2C0_RESET_ENABLE {0} \
304. CONFIG.PCW_I2C1_RESET_ENABLE {0} \
305. CONFIG.PCW_I2C_PERIPHERAL_FREQMHZ {25} \
306. CONFIG.PCW_I2C_RESET_ENABLE {1} \
307. CONFIG.PCW_IOPLL_CTRL_FBDIV {30} \
308. CONFIG.PCW_IO_IO_PLL_FREQMHZ {1000.000} \
309. CONFIG.PCW_IRQ_F2P_MODE {DIRECT} \
310. CONFIG.PCW_MIO_0_DIRECTION {inout} \
311. CONFIG.PCW_MIO_0_IOTYPE {LVCMOS 3.3V} \
312. CONFIG.PCW_MIO_0_PULLUP {enabled} \
313. CONFIG.PCW_MIO_0_SLEW {slow} \
314. CONFIG.PCW_MIO_10_DIRECTION {inout} \
315. CONFIG.PCW_MIO_10_IOTYPE {LVCMOS 3.3V} \
316. CONFIG.PCW_MIO_10_PULLUP {enabled} \
317. CONFIG.PCW_MIO_10_SLEW {slow} \
318. CONFIG.PCW_MIO_11_DIRECTION {inout} \
319. CONFIG.PCW_MIO_11_IOTYPE {LVCMOS 3.3V} \
320. CONFIG.PCW_MIO_11_PULLUP {enabled} \
321. CONFIG.PCW_MIO_11_SLEW {slow} \
322. CONFIG.PCW_MIO_12_DIRECTION {inout} \
323. CONFIG.PCW_MIO_12_IOTYPE {LVCMOS 3.3V} \
324. CONFIG.PCW_MIO_12_PULLUP {enabled} \
325. CONFIG.PCW_MIO_12_SLEW {slow} \
326. CONFIG.PCW_MIO_13_DIRECTION {inout} \
327. CONFIG.PCW_MIO_13_IOTYPE {LVCMOS 3.3V} \
328. CONFIG.PCW_MIO_13_PULLUP {enabled} \
329. CONFIG.PCW_MIO_13_SLEW {slow} \
330. CONFIG.PCW_MIO_14_DIRECTION {inout} \
331. CONFIG.PCW_MIO_14_IOTYPE {LVCMOS 3.3V} \
332. CONFIG.PCW_MIO_14_PULLUP {enabled} \
333. CONFIG.PCW_MIO_14_SLEW {slow} \
334. CONFIG.PCW_MIO_15_DIRECTION {inout} \
335. CONFIG.PCW_MIO_15_IOTYPE {LVCMOS 3.3V} \
336. CONFIG.PCW_MIO_15_PULLUP {enabled} \
337. CONFIG.PCW_MIO_15_SLEW {slow} \
338. CONFIG.PCW_MIO_16_DIRECTION {out} \
339. CONFIG.PCW_MIO_16_IOTYPE {LVCMOS 1.8V} \
340. CONFIG.PCW_MIO_16_PULLUP {enabled} \
341. CONFIG.PCW_MIO_16_SLEW {fast} \
342. CONFIG.PCW_MIO_17_DIRECTION {out} \
343. CONFIG.PCW_MIO_17_IOTYPE {LVCMOS 1.8V} \
344. CONFIG.PCW_MIO_17_PULLUP {enabled} \
345. CONFIG.PCW_MIO_17_SLEW {fast} \
346. CONFIG.PCW_MIO_18_DIRECTION {out} \
347. CONFIG.PCW_MIO_18_IOTYPE {LVCMOS 1.8V} \
348. CONFIG.PCW_MIO_18_PULLUP {enabled} \
349. CONFIG.PCW_MIO_18_SLEW {fast} \
350. CONFIG.PCW_MIO_19_DIRECTION {out} \
351. CONFIG.PCW_MIO_19_IOTYPE {LVCMOS 1.8V} \
352. CONFIG.PCW_MIO_19_PULLUP {enabled} \
353. CONFIG.PCW_MIO_19_SLEW {fast} \
354. CONFIG.PCW_MIO_1_DIRECTION {out} \
355. CONFIG.PCW_MIO_1_IOTYPE {LVCMOS 3.3V} \
356. CONFIG.PCW_MIO_1_PULLUP {enabled} \
357. CONFIG.PCW_MIO_1_SLEW {slow} \
358. CONFIG.PCW_MIO_20_DIRECTION {out} \
359. CONFIG.PCW_MIO_20_IOTYPE {LVCMOS 1.8V} \
360. CONFIG.PCW_MIO_20_PULLUP {enabled} \
361. CONFIG.PCW_MIO_20_SLEW {fast} \
362. CONFIG.PCW_MIO_21_DIRECTION {out} \
363. CONFIG.PCW_MIO_21_IOTYPE {LVCMOS 1.8V} \
364. CONFIG.PCW_MIO_21_PULLUP {enabled} \
365. CONFIG.PCW_MIO_21_SLEW {fast} \
366. CONFIG.PCW_MIO_22_DIRECTION {in} \
367. CONFIG.PCW_MIO_22_IOTYPE {LVCMOS 1.8V} \
368. CONFIG.PCW_MIO_22_PULLUP {enabled} \
369. CONFIG.PCW_MIO_22_SLEW {fast} \
370. CONFIG.PCW_MIO_23_DIRECTION {in} \
371. CONFIG.PCW_MIO_23_IOTYPE {LVCMOS 1.8V} \
372. CONFIG.PCW_MIO_23_PULLUP {enabled} \
373. CONFIG.PCW_MIO_23_SLEW {fast} \
374. CONFIG.PCW_MIO_24_DIRECTION {in} \
375. CONFIG.PCW_MIO_24_IOTYPE {LVCMOS 1.8V} \
376. CONFIG.PCW_MIO_24_PULLUP {enabled} \
377. CONFIG.PCW_MIO_24_SLEW {fast} \
378. CONFIG.PCW_MIO_25_DIRECTION {in} \
379. CONFIG.PCW_MIO_25_IOTYPE {LVCMOS 1.8V} \
380. CONFIG.PCW_MIO_25_PULLUP {enabled} \
381. CONFIG.PCW_MIO_25_SLEW {fast} \
382. CONFIG.PCW_MIO_26_DIRECTION {in} \
383. CONFIG.PCW_MIO_26_IOTYPE {LVCMOS 1.8V} \
384. CONFIG.PCW_MIO_26_PULLUP {enabled} \
385. CONFIG.PCW_MIO_26_SLEW {fast} \
386. CONFIG.PCW_MIO_27_DIRECTION {in} \
387. CONFIG.PCW_MIO_27_IOTYPE {LVCMOS 1.8V} \
388. CONFIG.PCW_MIO_27_PULLUP {enabled} \
389. CONFIG.PCW_MIO_27_SLEW {fast} \
390. CONFIG.PCW_MIO_28_DIRECTION {inout} \
391. CONFIG.PCW_MIO_28_IOTYPE {LVCMOS 1.8V} \
392. CONFIG.PCW_MIO_28_PULLUP {enabled} \
393. CONFIG.PCW_MIO_28_SLEW {fast} \
394. CONFIG.PCW_MIO_29_DIRECTION {in} \
395. CONFIG.PCW_MIO_29_IOTYPE {LVCMOS 1.8V} \
396. CONFIG.PCW_MIO_29_PULLUP {enabled} \
397. CONFIG.PCW_MIO_29_SLEW {fast} \
398. CONFIG.PCW_MIO_2_DIRECTION {inout} \
399. CONFIG.PCW_MIO_2_IOTYPE {LVCMOS 3.3V} \
400. CONFIG.PCW_MIO_2_PULLUP {disabled} \
401. CONFIG.PCW_MIO_2_SLEW {slow} \
402. CONFIG.PCW_MIO_30_DIRECTION {out} \
403. CONFIG.PCW_MIO_30_IOTYPE {LVCMOS 1.8V} \
404. CONFIG.PCW_MIO_30_PULLUP {enabled} \
405. CONFIG.PCW_MIO_30_SLEW {fast} \
406. CONFIG.PCW_MIO_31_DIRECTION {in} \
407. CONFIG.PCW_MIO_31_IOTYPE {LVCMOS 1.8V} \
408. CONFIG.PCW_MIO_31_PULLUP {enabled} \
409. CONFIG.PCW_MIO_31_SLEW {fast} \
410. CONFIG.PCW_MIO_32_DIRECTION {inout} \
411. CONFIG.PCW_MIO_32_IOTYPE {LVCMOS 1.8V} \
412. CONFIG.PCW_MIO_32_PULLUP {enabled} \
413. CONFIG.PCW_MIO_32_SLEW {fast} \
414. CONFIG.PCW_MIO_33_DIRECTION {inout} \
415. CONFIG.PCW_MIO_33_IOTYPE {LVCMOS 1.8V} \
416. CONFIG.PCW_MIO_33_PULLUP {enabled} \
417. CONFIG.PCW_MIO_33_SLEW {fast} \
418. CONFIG.PCW_MIO_34_DIRECTION {inout} \
419. CONFIG.PCW_MIO_34_IOTYPE {LVCMOS 1.8V} \
420. CONFIG.PCW_MIO_34_PULLUP {enabled} \
421. CONFIG.PCW_MIO_34_SLEW {fast} \
422. CONFIG.PCW_MIO_35_DIRECTION {inout} \
423. CONFIG.PCW_MIO_35_IOTYPE {LVCMOS 1.8V} \
424. CONFIG.PCW_MIO_35_PULLUP {enabled} \
425. CONFIG.PCW_MIO_35_SLEW {fast} \
426. CONFIG.PCW_MIO_36_DIRECTION {in} \
427. CONFIG.PCW_MIO_36_IOTYPE {LVCMOS 1.8V} \
428. CONFIG.PCW_MIO_36_PULLUP {enabled} \
429. CONFIG.PCW_MIO_36_SLEW {fast} \
430. CONFIG.PCW_MIO_37_DIRECTION {inout} \
431. CONFIG.PCW_MIO_37_IOTYPE {LVCMOS 1.8V} \
432. CONFIG.PCW_MIO_37_PULLUP {enabled} \
433. CONFIG.PCW_MIO_37_SLEW {fast} \
434. CONFIG.PCW_MIO_38_DIRECTION {inout} \
435. CONFIG.PCW_MIO_38_IOTYPE {LVCMOS 1.8V} \
436. CONFIG.PCW_MIO_38_PULLUP {enabled} \
437. CONFIG.PCW_MIO_38_SLEW {fast} \
438. CONFIG.PCW_MIO_39_DIRECTION {inout} \
439. CONFIG.PCW_MIO_39_IOTYPE {LVCMOS 1.8V} \
440. CONFIG.PCW_MIO_39_PULLUP {enabled} \
441. CONFIG.PCW_MIO_39_SLEW {fast} \
442. CONFIG.PCW_MIO_3_DIRECTION {inout} \
443. CONFIG.PCW_MIO_3_IOTYPE {LVCMOS 3.3V} \
444. CONFIG.PCW_MIO_3_PULLUP {disabled} \
445. CONFIG.PCW_MIO_3_SLEW {slow} \
446. CONFIG.PCW_MIO_40_DIRECTION {inout} \
447. CONFIG.PCW_MIO_40_IOTYPE {LVCMOS 1.8V} \
448. CONFIG.PCW_MIO_40_PULLUP {enabled} \
449. CONFIG.PCW_MIO_40_SLEW {slow} \
450. CONFIG.PCW_MIO_41_DIRECTION {inout} \
451. CONFIG.PCW_MIO_41_IOTYPE {LVCMOS 1.8V} \
452. CONFIG.PCW_MIO_41_PULLUP {enabled} \
453. CONFIG.PCW_MIO_41_SLEW {slow} \
454. CONFIG.PCW_MIO_42_DIRECTION {inout} \
455. CONFIG.PCW_MIO_42_IOTYPE {LVCMOS 1.8V} \
456. CONFIG.PCW_MIO_42_PULLUP {enabled} \
457. CONFIG.PCW_MIO_42_SLEW {slow} \
458. CONFIG.PCW_MIO_43_DIRECTION {inout} \
459. CONFIG.PCW_MIO_43_IOTYPE {LVCMOS 1.8V} \
460. CONFIG.PCW_MIO_43_PULLUP {enabled} \
461. CONFIG.PCW_MIO_43_SLEW {slow} \
462. CONFIG.PCW_MIO_44_DIRECTION {inout} \
463. CONFIG.PCW_MIO_44_IOTYPE {LVCMOS 1.8V} \
464. CONFIG.PCW_MIO_44_PULLUP {enabled} \
465. CONFIG.PCW_MIO_44_SLEW {slow} \
466. CONFIG.PCW_MIO_45_DIRECTION {inout} \
467. CONFIG.PCW_MIO_45_IOTYPE {LVCMOS 1.8V} \
468. CONFIG.PCW_MIO_45_PULLUP {enabled} \
469. CONFIG.PCW_MIO_45_SLEW {slow} \
470. CONFIG.PCW_MIO_46_DIRECTION {out} \
471. CONFIG.PCW_MIO_46_IOTYPE {LVCMOS 1.8V} \
472. CONFIG.PCW_MIO_46_PULLUP {enabled} \
473. CONFIG.PCW_MIO_46_SLEW {slow} \
474. CONFIG.PCW_MIO_47_DIRECTION {in} \
475. CONFIG.PCW_MIO_47_IOTYPE {LVCMOS 1.8V} \
476. CONFIG.PCW_MIO_47_PULLUP {enabled} \
477. CONFIG.PCW_MIO_47_SLEW {slow} \
478. CONFIG.PCW_MIO_48_DIRECTION {out} \
479. CONFIG.PCW_MIO_48_IOTYPE {LVCMOS 1.8V} \
480. CONFIG.PCW_MIO_48_PULLUP {enabled} \
481. CONFIG.PCW_MIO_48_SLEW {slow} \
482. CONFIG.PCW_MIO_49_DIRECTION {in} \
483. CONFIG.PCW_MIO_49_IOTYPE {LVCMOS 1.8V} \
484. CONFIG.PCW_MIO_49_PULLUP {enabled} \
485. CONFIG.PCW_MIO_49_SLEW {slow} \
486. CONFIG.PCW_MIO_4_DIRECTION {inout} \
487. CONFIG.PCW_MIO_4_IOTYPE {LVCMOS 3.3V} \
488. CONFIG.PCW_MIO_4_PULLUP {disabled} \
489. CONFIG.PCW_MIO_4_SLEW {slow} \
490. CONFIG.PCW_MIO_50_DIRECTION {inout} \
491. CONFIG.PCW_MIO_50_IOTYPE {LVCMOS 1.8V} \
492. CONFIG.PCW_MIO_50_PULLUP {enabled} \
493. CONFIG.PCW_MIO_50_SLEW {slow} \
494. CONFIG.PCW_MIO_51_DIRECTION {inout} \
495. CONFIG.PCW_MIO_51_IOTYPE {LVCMOS 1.8V} \
496. CONFIG.PCW_MIO_51_PULLUP {enabled} \
497. CONFIG.PCW_MIO_51_SLEW {slow} \
498. CONFIG.PCW_MIO_52_DIRECTION {out} \
499. CONFIG.PCW_MIO_52_IOTYPE {LVCMOS 1.8V} \
500. CONFIG.PCW_MIO_52_PULLUP {enabled} \
501. CONFIG.PCW_MIO_52_SLEW {slow} \
502. CONFIG.PCW_MIO_53_DIRECTION {inout} \
503. CONFIG.PCW_MIO_53_IOTYPE {LVCMOS 1.8V} \
504. CONFIG.PCW_MIO_53_PULLUP {enabled} \
505. CONFIG.PCW_MIO_53_SLEW {slow} \
506. CONFIG.PCW_MIO_5_DIRECTION {inout} \
507. CONFIG.PCW_MIO_5_IOTYPE {LVCMOS 3.3V} \
508. CONFIG.PCW_MIO_5_PULLUP {disabled} \
509. CONFIG.PCW_MIO_5_SLEW {slow} \
510. CONFIG.PCW_MIO_6_DIRECTION {out} \
511. CONFIG.PCW_MIO_6_IOTYPE {LVCMOS 3.3V} \
512. CONFIG.PCW_MIO_6_PULLUP {disabled} \
513. CONFIG.PCW_MIO_6_SLEW {slow} \
514. CONFIG.PCW_MIO_7_DIRECTION {out} \
515. CONFIG.PCW_MIO_7_IOTYPE {LVCMOS 3.3V} \
516. CONFIG.PCW_MIO_7_PULLUP {disabled} \
517. CONFIG.PCW_MIO_7_SLEW {slow} \
518. CONFIG.PCW_MIO_8_DIRECTION {out} \
519. CONFIG.PCW_MIO_8_IOTYPE {LVCMOS 3.3V} \
520. CONFIG.PCW_MIO_8_PULLUP {disabled} \
521. CONFIG.PCW_MIO_8_SLEW {slow} \
522. CONFIG.PCW_MIO_9_DIRECTION {inout} \
523. CONFIG.PCW_MIO_9_IOTYPE {LVCMOS 3.3V} \
524. CONFIG.PCW_MIO_9_PULLUP {enabled} \
525. CONFIG.PCW_MIO_9_SLEW {slow} \
526. CONFIG.PCW_MIO_TREE_PERIPHERALS { \
527. 0#Enet 0 \
528. 0#Enet 0 \
529. 0#Enet 0 \
530. 0#Enet 0 \
531. 0#Enet 0 \
532. 0#Enet 0 \
533. 0#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#SD 0#SD \
534. 0#GPIO#SD 0#UART \
535. 0#SD 0#SD \
536. 0#SD 0#SD \
537. 1#UART 1#GPIO#GPIO#Enet \
538. Flash#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#Enet 0#Enet \
539. Flash#GPIO#Quad SPI \
540. Flash#Quad SPI \
541. Flash#Quad SPI \
542. Flash#Quad SPI \
543. Flash#Quad SPI \
544. Flash#Quad SPI \
545. GPIO#Quad SPI \
546. } \
547. CONFIG.PCW_MIO_TREE_SIGNALS {gpio⁰#qspi0_ss_b#qspi0_io⁰#qspi0_io¹#qspi0_io²#qspi0_io³/HOLD_B#qspi0_sclk#gpio⁷#qspi_fbclk#gpio⁹#gpio¹⁰#gpio¹¹#gpio¹²#gpio¹³#gpio¹⁴#gpio¹⁵#tx_clk#txd⁰#txd¹#txd²#txd³#tx_ctl#rx_clk#rxd⁰#rxd¹#rxd²#rxd³#rx_ctl#gpio²⁸#gpio²⁹#gpio³⁰#gpio³¹#gpio³²#gpio³³#gpio³⁴#gpio³⁵#gpio³⁶#gpio³⁷#gpio³⁸#gpio³⁹#clk#cmd#data⁰#data¹#data²#data³#gpio⁴⁶#cd#tx#rx#gpio⁵⁰#gpio⁵¹#mdc#mdio} \
548. CONFIG.PCW_NAND_GRP_D8_ENABLE {0} \
549. CONFIG.PCW_NAND_PERIPHERAL_ENABLE {0} \
550. CONFIG.PCW_NOR_GRP_A25_ENABLE {0} \
551. CONFIG.PCW_NOR_GRP_CS0_ENABLE {0} \
552. CONFIG.PCW_NOR_GRP_CS1_ENABLE {0} \
553. CONFIG.PCW_NOR_GRP_SRAM_CS0_ENABLE {0} \
554. CONFIG.PCW_NOR_GRP_SRAM_CS1_ENABLE {0} \
555. CONFIG.PCW_NOR_GRP_SRAM_INT_ENABLE {0} \
556. CONFIG.PCW_NOR_PERIPHERAL_ENABLE {0} \
557. CONFIG.PCW_OVERRIDE_BASIC_CLOCK {0} \
558. CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY0 {0.221} \
559. CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY1 {0.222} \
560. CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY2 {0.217} \
561. CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY3 {0.244} \
562. CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_0 {-0.050} \
563. CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_1 {-0.044} \
564. CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_2 {-0.035} \
565. CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_3 {-0.100} \
566. CONFIG.PCW_PCAP_PERIPHERAL_CLKSRC {IO PLL} \
567. CONFIG.PCW_PCAP_PERIPHERAL_DIVISOR0 {5} \
568. CONFIG.PCW_PCAP_PERIPHERAL_FREQMHZ {200} \
569. CONFIG.PCW_PJTAG_PERIPHERAL_ENABLE {0} \
570. CONFIG.PCW_PLL_BYPASSMODE_ENABLE {0} \
571. CONFIG.PCW_PRESET_BANK0_VOLTAGE {LVCMOS 3.3V} \
572. CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 1.8V} \
573. CONFIG.PCW_QSPI_GRP_FBCLK_ENABLE {1} \
574. CONFIG.PCW_QSPI_GRP_FBCLK_IO {MIO 8} \
575. CONFIG.PCW_QSPI_GRP_IO1_ENABLE {0} \
576. CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE {1} \
577. CONFIG.PCW_QSPI_GRP_SINGLE_SS_IO {MIO 1 .. 6} \
578. CONFIG.PCW_QSPI_GRP_SS1_ENABLE {0} \
579. CONFIG.PCW_QSPI_INTERNAL_HIGHADDRESS {0xFCFFFFFF} \
580. CONFIG.PCW_QSPI_PERIPHERAL_CLKSRC {IO PLL} \
581. CONFIG.PCW_QSPI_PERIPHERAL_DIVISOR0 {5} \
582. CONFIG.PCW_QSPI_PERIPHERAL_ENABLE {1} \
583. CONFIG.PCW_QSPI_PERIPHERAL_FREQMHZ {200} \
584. CONFIG.PCW_QSPI_QSPI_IO {MIO 1 .. 6} \
585. CONFIG.PCW_SD0_GRP_CD_ENABLE {1} \
586. CONFIG.PCW_SD0_GRP_CD_IO {MIO 47} \
587. CONFIG.PCW_SD0_GRP_POW_ENABLE {0} \
588. CONFIG.PCW_SD0_GRP_WP_ENABLE {0} \
589. CONFIG.PCW_SD0_PERIPHERAL_ENABLE {1} \
590. CONFIG.PCW_SD0_SD0_IO {MIO 40 .. 45} \
591. CONFIG.PCW_SDIO_PERIPHERAL_CLKSRC {IO PLL} \
592. CONFIG.PCW_SDIO_PERIPHERAL_DIVISOR0 {20} \
593. CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ {50} \
594. CONFIG.PCW_SDIO_PERIPHERAL_VALID {1} \
595. CONFIG.PCW_SINGLE_QSPI_DATA_MODE {x4} \
596. CONFIG.PCW_SMC_PERIPHERAL_CLKSRC {IO PLL} \
597. CONFIG.PCW_SMC_PERIPHERAL_DIVISOR0 {1} \
598. CONFIG.PCW_SMC_PERIPHERAL_FREQMHZ {100} \
599. CONFIG.PCW_SPI_PERIPHERAL_DIVISOR0 {1} \
600. CONFIG.PCW_TPIU_PERIPHERAL_CLKSRC {External} \
601. CONFIG.PCW_TPIU_PERIPHERAL_DIVISOR0 {1} \
602. CONFIG.PCW_TPIU_PERIPHERAL_FREQMHZ {200} \
603. CONFIG.PCW_UART0_GRP_FULL_ENABLE {0} \
604. CONFIG.PCW_UART0_PERIPHERAL_ENABLE {0} \
605. CONFIG.PCW_UART1_BAUD_RATE {115200} \
606. CONFIG.PCW_UART1_GRP_FULL_ENABLE {0} \
607. CONFIG.PCW_UART1_PERIPHERAL_ENABLE {1} \
608. CONFIG.PCW_UART1_UART1_IO {MIO 48 .. 49} \
609. CONFIG.PCW_UART_PERIPHERAL_CLKSRC {IO PLL} \
610. CONFIG.PCW_UART_PERIPHERAL_DIVISOR0 {10} \
611. CONFIG.PCW_UART_PERIPHERAL_FREQMHZ {100} \
612. CONFIG.PCW_UART_PERIPHERAL_VALID {1} \
613. CONFIG.PCW_UIPARAM_ACT_DDR_FREQ_MHZ {533.333374} \
614. CONFIG.PCW_UIPARAM_DDR_ADV_ENABLE {0} \
615. CONFIG.PCW_UIPARAM_DDR_AL {0} \
616. CONFIG.PCW_UIPARAM_DDR_BANK_ADDR_COUNT {3} \
617. CONFIG.PCW_UIPARAM_DDR_BL {8} \
618. CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0 {0.221} \
619. CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1 {0.222} \
620. CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2 {0.217} \
621. CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3 {0.244} \
622. CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH {32 Bit} \
623. CONFIG.PCW_UIPARAM_DDR_CL {7} \
624. CONFIG.PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM {18.8} \
625. CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH {80.4535} \
626. CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY {160} \
627. CONFIG.PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM {18.8} \
628. CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH {80.4535} \
629. CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY {160} \
630. CONFIG.PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM {18.8} \
631. CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH {80.4535} \
632. CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY {160} \
633. CONFIG.PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM {18.8} \
634. CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH {80.4535} \
635. CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY {160} \
636. CONFIG.PCW_UIPARAM_DDR_CLOCK_STOP_EN {0} \
637. CONFIG.PCW_UIPARAM_DDR_COL_ADDR_COUNT {10} \
638. CONFIG.PCW_UIPARAM_DDR_CWL {6} \
639. CONFIG.PCW_UIPARAM_DDR_DEVICE_CAPACITY {4096 MBits} \
640. CONFIG.PCW_UIPARAM_DDR_DQS_0_LENGTH_MM {22.8} \
641. CONFIG.PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH {105.056} \
642. CONFIG.PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY {160} \
643. CONFIG.PCW_UIPARAM_DDR_DQS_1_LENGTH_MM {27.9} \
644. CONFIG.PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH {66.904} \
645. CONFIG.PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY {160} \
646. CONFIG.PCW_UIPARAM_DDR_DQS_2_LENGTH_MM {22.9} \
647. CONFIG.PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH {89.1715} \
648. CONFIG.PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY {160} \
649. CONFIG.PCW_UIPARAM_DDR_DQS_3_LENGTH_MM {29.4} \
650. CONFIG.PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH {113.63} \
651. CONFIG.PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY {160} \
652. CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 {-0.050} \
653. CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 {-0.044} \
654. CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 {-0.035} \
655. CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 {-0.100} \
656. CONFIG.PCW_UIPARAM_DDR_DQ_0_LENGTH_MM {22.8} \
657. CONFIG.PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH {98.503} \
658. CONFIG.PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY {160} \
659. CONFIG.PCW_UIPARAM_DDR_DQ_1_LENGTH_MM {27.9} \
660. CONFIG.PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH {68.5855} \
661. CONFIG.PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY {160} \
662. CONFIG.PCW_UIPARAM_DDR_DQ_2_LENGTH_MM {22.9} \
663. CONFIG.PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH {90.295} \
664. CONFIG.PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY {160} \
665. CONFIG.PCW_UIPARAM_DDR_DQ_3_LENGTH_MM {29.4} \
666. CONFIG.PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH {103.977} \
667. CONFIG.PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY {160} \
668. CONFIG.PCW_UIPARAM_DDR_DRAM_WIDTH {16 Bits} \
669. CONFIG.PCW_UIPARAM_DDR_ECC {Disabled} \
670. CONFIG.PCW_UIPARAM_DDR_ENABLE {1} \
671. CONFIG.PCW_UIPARAM_DDR_FREQ_MHZ {533.333333} \
672. CONFIG.PCW_UIPARAM_DDR_HIGH_TEMP {Normal (0-85)} \
673. CONFIG.PCW_UIPARAM_DDR_MEMORY_TYPE {DDR 3 (Low Voltage)} \
674. CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41K256M16 RE-125} \
675. CONFIG.PCW_UIPARAM_DDR_ROW_ADDR_COUNT {15} \
676. CONFIG.PCW_UIPARAM_DDR_SPEED_BIN {DDR3_1066F} \
677. CONFIG.PCW_UIPARAM_DDR_TRAIN_DATA_EYE {1} \
678. CONFIG.PCW_UIPARAM_DDR_TRAIN_READ_GATE {1} \
679. CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL {1} \
680. CONFIG.PCW_UIPARAM_DDR_T_FAW {40.0} \
681. CONFIG.PCW_UIPARAM_DDR_T_RAS_MIN {35.0} \
682. CONFIG.PCW_UIPARAM_DDR_T_RC {48.75} \
683. CONFIG.PCW_UIPARAM_DDR_T_RCD {7} \
684. CONFIG.PCW_UIPARAM_DDR_T_RP {7} \
685. CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF {0} \
686. CONFIG.PCW_USB0_PERIPHERAL_ENABLE {0} \
687. CONFIG.PCW_USB0_PERIPHERAL_FREQMHZ {60} \
688. CONFIG.PCW_USB0_RESET_ENABLE {1} \
689. CONFIG.PCW_USB0_RESET_IO {MIO 46} \
690. CONFIG.PCW_USB0_USB0_IO {<Select>} \
691. CONFIG.PCW_USB1_RESET_ENABLE {0} \
692. CONFIG.PCW_USB_RESET_ENABLE {1} \
693. CONFIG.PCW_USB_RESET_POLARITY {Active Low} \
694. CONFIG.PCW_USB_RESET_SELECT {<Select>} \
695. CONFIG.PCW_USE_AXI_NONSECURE {0} \
696. CONFIG.PCW_USE_CROSS_TRIGGER {0} \
697. CONFIG.PCW_USE_M_AXI_GP0 {1} \
698. ] $processing_system7_0
700. # Create instance: ps7_0_axi_periph, and set properties
701. set ps7_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 ps7_0_axi_periph ]
702. set_property -dict [ list \
703. CONFIG.NUM_MI {1} \
704. ] $ps7_0_axi_periph
706. # Create instance: rst_ps7_0_50M, and set properties
707. set rst_ps7_0_50M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_ps7_0_50M ]
709. # Create instance: xadc_wiz_0, and set properties
710. set xadc_wiz_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xadc_wiz:3.3 xadc_wiz_0 ]
711. set_property -dict [ list \
712. CONFIG.ADC_OFFSET_AND_GAIN_CALIBRATION {false} \
713. CONFIG.CHANNEL_ENABLE_VAUXP14_VAUXN14 {true} \
714. CONFIG.CHANNEL_ENABLE_VAUXP15_VAUXN15 {true} \
715. CONFIG.CHANNEL_ENABLE_VAUXP6_VAUXN6 {true} \
716. CONFIG.CHANNEL_ENABLE_VAUXP7_VAUXN7 {true} \
717. CONFIG.CHANNEL_ENABLE_VP_VN {false} \
718. CONFIG.ENABLE_CALIBRATION_AVERAGING {false} \
719. CONFIG.ENABLE_VCCDDRO_ALARM {false} \
720. CONFIG.ENABLE_VCCPAUX_ALARM {false} \
721. CONFIG.ENABLE_VCCPINT_ALARM {false} \
722. CONFIG.EXTERNAL_MUX_CHANNEL {VP_VN} \
723. CONFIG.OT_ALARM {false} \
724. CONFIG.SENSOR_OFFSET_AND_GAIN_CALIBRATION {false} \
725. CONFIG.SEQUENCER_MODE {Continuous} \
726. CONFIG.SINGLE_CHANNEL_SELECTION {TEMPERATURE} \
727. CONFIG.USER_TEMP_ALARM {false} \
728. CONFIG.VCCAUX_ALARM {false} \
729. CONFIG.VCCINT_ALARM {false} \
730. CONFIG.XADC_STARUP_SELECTION {channel_sequencer} \
731. ] $xadc_wiz_0
733. # Create interface connections
734. connect_bd_intf_net -intf_net Vaux14_1 [get_bd_intf_ports Vaux14] [get_bd_intf_pins xadc_wiz_0/Vaux14]
735. connect_bd_intf_net -intf_net Vaux15_1 [get_bd_intf_ports Vaux15] [get_bd_intf_pins xadc_wiz_0/Vaux15]
736. connect_bd_intf_net -intf_net Vaux6_1 [get_bd_intf_ports Vaux6] [get_bd_intf_pins xadc_wiz_0/Vaux6]
737. connect_bd_intf_net -intf_net Vaux7_1 [get_bd_intf_ports Vaux7] [get_bd_intf_pins xadc_wiz_0/Vaux7]
738. connect_bd_intf_net -intf_net processing_system7_0_DDR [get_bd_intf_ports DDR] [get_bd_intf_pins processing_system7_0/DDR]
739. connect_bd_intf_net -intf_net processing_system7_0_FIXED_IO [get_bd_intf_ports FIXED_IO] [get_bd_intf_pins processing_system7_0/FIXED_IO]
740. connect_bd_intf_net -intf_net processing_system7_0_M_AXI_GP0 [get_bd_intf_pins processing_system7_0/M_AXI_GP0] [get_bd_intf_pins ps7_0_axi_periph/S00_AXI]
741. connect_bd_intf_net -intf_net ps7_0_axi_periph_M00_AXI [get_bd_intf_pins ps7_0_axi_periph/M00_AXI] [get_bd_intf_pins xadc_wiz_0/s_axi_lite]
743. # Create port connections
744. connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins ps7_0_axi_periph/ACLK] [get_bd_pins ps7_0_axi_periph/M00_ACLK] [get_bd_pins ps7_0_axi_periph/S00_ACLK] [get_bd_pins rst_ps7_0_50M/slowest_sync_clk] [get_bd_pins xadc_wiz_0/s_axi_aclk]
745. connect_bd_net -net processing_system7_0_FCLK_RESET0_N [get_bd_pins processing_system7_0/FCLK_RESET0_N] [get_bd_pins rst_ps7_0_50M/ext_reset_in]
746. connect_bd_net -net rst_ps7_0_50M_peripheral_aresetn [get_bd_pins ps7_0_axi_periph/ARESETN] [get_bd_pins ps7_0_axi_periph/M00_ARESETN] [get_bd_pins ps7_0_axi_periph/S00_ARESETN] [get_bd_pins rst_ps7_0_50M/peripheral_aresetn] [get_bd_pins xadc_wiz_0/s_axi_aresetn]
748. # Create address segments
749. assign_bd_address -offset 0x43C00000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs xadc_wiz_0/s_axi_lite/Reg] -force
751. # Perform GUI Layout
752. regenerate_bd_layout -layout_string {
753. "ActiveEmotionalView":"Default View",
754. "Default View_ScaleFactor":"0.951852",
755. "Default View_TopLeft":"-139,30",
756. "ExpandedHierarchyInLayout":"",
757. "guistr":"# # String gsaved with Nlview 7.0r6 2020-01-29 bk=1.5227 VDI=41 GEI=36 GUI=JA:10.0 non-TLS
758. # -string -flagsOSRD
759. preplace port DDR -pg 1 -lvl 4 -x 1080 -y 60 -defaultsOSRD
760. preplace port FIXED_IO -pg 1 -lvl 4 -x 1080 -y 80 -defaultsOSRD
761. preplace port Vaux6 -pg 1 -lvl 0 -x -10 -y 210 -defaultsOSRD
762. preplace port Vaux7 -pg 1 -lvl 0 -x -10 -y 420 -defaultsOSRD
763. preplace port Vaux14 -pg 1 -lvl 0 -x -10 -y 470 -defaultsOSRD
764. preplace port Vaux15 -pg 1 -lvl 0 -x -10 -y 490 -defaultsOSRD
765. preplace inst processing_system7_0 -pg 1 -lvl 1 -x 230 -y 100 -defaultsOSRD
766. preplace inst xadc_wiz_0 -pg 1 -lvl 3 -x 930 -y 410 -defaultsOSRD
767. preplace inst ps7_0_axi_periph -pg 1 -lvl 2 -x 610 -y 340 -defaultsOSRD
768. preplace inst rst_ps7_0_50M -pg 1 -lvl 1 -x 230 -y 320 -defaultsOSRD
769. preplace netloc processing_system7_0_FCLK_CLK0 1 0 3 20 430 440 480 790
770. preplace netloc processing_system7_0_FCLK_RESET0_N 1 0 2 30 420 430
771. preplace netloc rst_ps7_0_50M_peripheral_aresetn 1 1 2 450 500 800J
772. preplace netloc processing_system7_0_DDR 1 1 3 NJ 60 NJ 60 NJ
773. preplace netloc processing_system7_0_FIXED_IO 1 1 3 NJ 80 NJ 80 NJ
774. preplace netloc processing_system7_0_M_AXI_GP0 1 1 1 450 100n
775. preplace netloc ps7_0_axi_periph_M00_AXI 1 2 1 N 340
776. preplace netloc Vaux6_1 1 0 3 NJ 210 NJ 210 760J
777. preplace netloc Vaux7_1 1 0 3 10J 460 NJ 460 760J
778. preplace netloc Vaux14_1 1 0 3 NJ 470 NJ 470 770J
779. preplace netloc Vaux15_1 1 0 3 NJ 490 NJ 490 780J
780. levelinfo -pg 1 -10 230 610 930 1080
781. pagesize -pg 1 -db -bbox -sgen -110 0 1200 540
782. "
783. }
785. # Restore current instance
786. current_bd_instance $oldCurInst
788. validate_bd_design
789. save_bd_design
790. close_bd_design $design_name
791. }
792. cr_bd_design_1 ""
     INFO: [BD::TCL 103-2010] Currently there is no design <design_1> in project, so creating one...
     Wrote : <C:\AimaginProjects\Z7000\adc_demo\hardware_design\vivado_tcl\adc_demo\adc_demo.srcs\sources_1\bd\design_1\design_1.bd>
     create_bd_design: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 1138.055 ; gain = 0.000
     INFO: [BD::TCL 103-2011] Checking if the following IPs exist in the project's IP catalog:
     xilinx.com:ip:processing_system7:5.5 xilinx.com:ip:proc_sys_reset:5.0 xilinx.com:ip:xadc_wiz:3.3 .
     WARNING: [IP_Flow 19-3331] Invalid parameters found in dependency constraints of 'ADDRBLOCK_RANGE.S_AXI_ACP.ACP_QSPI_LINEAR'
     WARNING: [IP_Flow 19-3331] Invalid parameters found in dependency constraints of 'ADDRBLOCK_RANGE.S_AXI_ACP.ACP_QSPI_LINEAR'
     WARNING: [IP_Flow 19-3553] Error found in parameter dependencies in XGUI files.
     ERROR: [IP_Flow 19-3428] Failed to create Customization object design_1_processing_system7_0_0
     CRITICAL WARNING: [IP_Flow 19-5622] Failed to create IP instance 'design_1_processing_system7_0_0'. Failed to customize IP instance 'design_1_processing_system7_0_0'. Failed to load customization data
     ERROR: [BD 41-1712] Create IP failed with errors
     ERROR: [BD 5-7] Error: running create_bd_cell -vlnv xilinx.com:ip:processing_system7:5.5 -type ip -name processing_system7_0 .
     ERROR: [Common 17-39] 'create_bd_cell' failed due to earlier errors.

     while executing
     "create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0 "
     (procedure "cr_bd_design_1" line 85)
     invoked from within
     "cr_bd_design_1 """
     (file "zybo7z20_adc_demo.tcl" line 885)
     update_compile_order -fileset sources_1

Any suggestions about what went wrong?
Regards,
johan.

Hi Johan,

It looks like the tcl script is failing when it is trying to add an IP core to the design.
Two of the probable causes for this would be,
1) Something is wrong with the installation (files not installed/ not in the expect location etc.)
2) certain settings in the operating system is causing this issue

First, please try to create a design in vivado manually, without using the tcl.
If this produces errors (errors will pop up on the tcl window when adding the ip block etc.), then this confirms above two reasons as the most probable causes.
At this stage it is a problem with vivado itself not the tcl file. Best approach here would be to seek help and information from xilinx support. https://support.xilinx.com/s/?language=en_US

From my brief research on xilinx forums, there are 2 things you can try. Please note these are suggestions that you may try at your own risk. As mentioned before, best step would be to ask xilinx support .
1) open the run window (Ctrl+R) and run "intl.cpl". (This is a solution I found on the xilinx forums. https://support.xilinx.com/s/question/0D52E00006hpkZlSAI/re-fails-to-load-include-zynq7-processing-system-ip-in-block-design?language=en_US)
In the window that pops up select "Change system locale"

Deselect Beta tick box and make sure the system locale is set to English (United States)

This has fixed this issue for some users.

2) Alternatively you can try reinstalling vivado (if you suspect there is a chance some options were not selected during installation and might be causing this issue)

If you are uncomfortable making changes to the operating system or need an explanation as to what exactly is the cause of this issue, it would be best to approach xilinx with this inquiry. If you do decide to do that, please keep us informed of your findings as well.

Best Regards,
Shawn

Hello Shawn,

I tried generating a project from scratch -> no success
Then I uninstallen and reinstalled Xilinx and added the boards again (version 1.0, not version 1.1)
Same problem occurred
Then I tried the work-around that you pointed me to (turning off the Beta checkbox was the only thing I needed to do)
Then it worked. GREAT!!! Thanks for helping me to find the right direction.

A few notes/questions:
1. running the .tcl script does not generate the .xsa file, I had to do a final step (File -> Export -> Export Hardware -> ...). Is that normal? Then is shall be in the readme.txt file.
2. there are still some warnings in the Tcl Console, is that normal? Do you see them also? I will list them below.
3. maybe the combination Windows 11 and Xilinx 2020 is not optimal. At a certain point in time I think it is better to switch to the latest version of Xilinx and the board files or the version just befor the latest. What is your opinion?

Here are the warnings in the TCL console:
WARNING: [Vivado 12-818] No files matched 'xdc/Zybo-Z7-Master.xdc'
WARNING: [Vivado 12-818] No files matched 'xdc/Zybo-Z7-Master.xdc'
CRITICAL WARNING: [PSU-1] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.050 . PS DDR interfaces might fail when entering negative DQS skew values.
CRITICAL WARNING: [PSU-2] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.044 . PS DDR interfaces might fail when entering negative DQS skew values.
CRITICAL WARNING: [PSU-3] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 has negative value -0.035 . PS DDR interfaces might fail when entering negative DQS skew values.
CRITICAL WARNING: [PSU-4] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 has negative value -0.100 . PS DDR interfaces might fail when entering negative DQS skew values.
CRITICAL WARNING: [PSU-1] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.050 . PS DDR interfaces might fail when entering negative DQS skew values.
CRITICAL WARNING: [PSU-2] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.044 . PS DDR interfaces might fail when entering negative DQS skew values.
CRITICAL WARNING: [PSU-3] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 has negative value -0.035 . PS DDR interfaces might fail when entering negative DQS skew values.
CRITICAL WARNING: [PSU-4] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 has negative value -0.100 . PS DDR interfaces might fail when entering negative DQS skew values.
CRITICAL WARNING: [PSU-1] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.050 . PS DDR interfaces might fail when entering negative DQS skew values.
CRITICAL WARNING: [PSU-2] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.044 . PS DDR interfaces might fail when entering negative DQS skew values.
CRITICAL WARNING: [PSU-3] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 has negative value -0.035 . PS DDR interfaces might fail when entering negative DQS skew values.
CRITICAL WARNING: [PSU-4] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 has negative value -0.100 . PS DDR interfaces might fail when entering negative DQS skew values.
WARNING: [BD 41-927] Following properties on pin /xadc_wiz_0/s_axi_aclk have been updated from connected ip, but BD cell '/xadc_wiz_0' does not accept parameter changes, so they may not be synchronized with cell properties:
FREQ_HZ = 50000000
Please resolve any mismatches by directly setting properties on BD cell </xadc_wiz_0> to completely resolve these warnings.
WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'M_AXI_GP0'. A default connection has been created.
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'c:/AimaginProjects/Z7000/adc_demo/hardware_design/vivado_tcl/adc_demo/adc_demo.gen/sources_1/bd/design_1/ip/design_1_auto_pc_0/design_1_auto_pc_0_ooc.xdc'
WARNING: [Project 1-645] Board images not set in Hardware Platform.

Regards,
johan.

Hi Johan,

Thank you for the feedback.

1. It seems the final step of generating the xsa file is not mentioned in the readme file. We will include that in future releases.
2. Yes. We also see these warnings. The warning related to the xdc file should not normally be there. We will look into the cause of that warning.
The critical warnings are related to vivado. You can get further info here (https://forum.digilent.com/topic/21356-getting-warnings-while-creating-vivado-project-with-zynq-boards/)
3. Yes. We will update the version of vivado/xilinx to a stable up to date version at a certain point in time.

If you look at the link I shared earlier ( https://support.xilinx.com/s/question/0D52E00006hpkZlSAI/re-fails-to-load-include-zynq7-processing-system-ip-in-block-design?language=en_US) that user is using windows 10 (released in 2015) with vivado 2018.
Considering after 2 years (vivado 2020) the error is still present, chances are very small that updating vivado would fix the issue you were facing.

Best Regards,
Shawn

Hi Johan,
You must put the TCL commands in the TCL console at the bottom of the screen, don't use the "Tools | Run TCL script..." command from the top menu bar.
When using the console at the bottom, everything is running without errors.
Best regards,

Martin.