Forums » Req. WJ2(Zynq-7000) support »
Errors when generating .xsa file (adc_demo project)
Added by Johan Henning over 1 year ago
This is what I did:
Followed the instructions.
Checked if the board was available:
issued the command: get_board_parts zybo
result: digilentinc.com:zybo-z7-10:part0:1.1 digilentinc.com:zybo-z7-20:part0:1.1 digilentinc.com:zybo:part0:1.0 digilentinc.com:zybo:part0:2.0
changed to directory of .tcl file
issued the command: source zybo7z20_adc_demo.tcl
This results in the following logfile and dialogs:
get_board_parts zybo
digilentinc.com:zybo-z7-10:part0:1.1 digilentinc.com:zybo-z7-20:part0:1.1 digilentinc.com:zybo:part0:1.0 digilentinc.com:zybo:part0:2.0
- proc checkRequiredFiles { origin_dir} {
- set status true
- set files [list \
- "xdc/Zybo-Z7-Master.xdc" \
- ]
- foreach ifile $files {
- if { ![file isfile $ifile] } {
- puts " Could not find local file $ifile "
- set status false
- }
- }
- return $status
- }
- set origin_dir "."
- if { [info exists ::origin_dir_loc] } {
- set origin_dir $::origin_dir_loc
- }
- set xil_proj_name "adc_demo"
- if { [info exists ::user_project_name] } {
- set xil_proj_name $::user_project_name
- }
- variable script_file
- set script_file "zybo7z20_adc_demo.tcl"
- proc print_help {} {
- variable script_file
- puts "\nDescription:"
- puts "Recreate a Vivado project from this script. The created project will be"
- puts "functionally equivalent to the original project for which this script was"
- puts "generated. The script contains commands for creating a project, filesets,"
- puts "runs, adding/importing sources and setting properties on various objects.\n"
- puts "Syntax:"
- puts "$script_file"
- puts "$script_file -tclargs \[--origin_dir <path>\]"
- puts "$script_file -tclargs \[--project_name <name>\]"
- puts "$script_file -tclargs \[--help\]\n"
- puts "Usage:"
- puts "Name Description"
- puts "-------------------------------------------------------------------------"
- puts "\[--origin_dir <path>\] Determine source file paths wrt this path. Default"
- puts " origin_dir path value is \".\", otherwise, the value"
- puts " that was set with the \"-paths_relative_to\" switch"
- puts " when this script was generated.\n"
- puts "\[--project_name <name>\] Create project with the specified name. Default"
- puts " name is the name of the project from where this"
- puts " script was generated.\n"
- puts "\[--help\] Print help information for this script"
- puts "-------------------------------------------------------------------------\n"
- exit 0
- }
- if { $::argc > 0 } {
- for {set i 0} {$i < $::argc} {incr i} {
- set option [string trim [lindex $::argv $i]]
- switch
regexp -$option { - "--origin_dir" { incr i; set origin_dir [lindex $::argv $i] }
- "--project_name" { incr i; set xil_proj_name [lindex $::argv $i] }
- "--help" { print_help }
- default {
- if { [regexp {^-} $option] } {
- puts "ERROR: Unknown option '$option' specified, please type '$script_file -tclargs --help' for usage info.\n"
- return 1
- }
- }
- }
- }
- }
- set orig_proj_dir "[file normalize "$origin_dir/adc_demo"]"
- set validate_required 0
- if { $validate_required } {
- if { [checkRequiredFiles $origin_dir] } {
- puts "Tcl file $script_file is valid. All files required for project creation is accesable. "
- } else {
- puts "Tcl file $script_file is not valid. Not all files required for project creation is accesable. "
- return
- }
- }
- create_project ${_xil_proj_name_} ./${_xil_proj_name_} -part xc7z020clg400-1
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2020.2/data/ip'. - set proj_dir [get_property directory [current_project]]
- set obj [current_project]
- set_property -name "board_part" -value "digilentinc.com:zybo-z7-20:part0:1.1" -objects $obj
- set_property -name "default_lib" -value "xil_defaultlib" -objects $obj
- set_property -name "enable_vhdl_2008" -value "1" -objects $obj
- set_property -name "ip_cache_permissions" -value "read write" -objects $obj
- set_property -name "ip_output_repo" -value "$proj_dir/${_xil_proj_name_}.cache/ip" -objects $obj
- set_property -name "mem.enable_memory_map_generation" -value "1" -objects $obj
- set_property -name "platform.board_id" -value "zybo-z7-20" -objects $obj
- set_property -name "sim.central_dir" -value "$proj_dir/${_xil_proj_name_}.ip_user_files" -objects $obj
- set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj
- set_property -name "simulator_language" -value "Mixed" -objects $obj
- set_property -name "xpm_libraries" -value "XPM_CDC XPM_MEMORY" -objects $obj
- if {[string equal [get_filesets -quiet sources_1] ""]} {
- create_fileset -srcset sources_1
- }
- set obj [get_filesets sources_1]
- set obj [get_filesets sources_1]
- set_property -name "top" -value "design_1_wrapper" -objects $obj
- if {[string equal [get_filesets -quiet constrs_1] ""]} {
- create_fileset -constrset constrs_1
- }
- set obj [get_filesets constrs_1]
- set file "[file normalize "xdc/Zybo-Z7-Master.xdc"]"
- set file_imported [import_files -fileset constrs_1 [list $file]]
- set file "xdc/Zybo-Z7-Master.xdc"
- set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]]
- set_property -name "file_type" -value "XDC" -objects $file_obj
- set obj [get_filesets constrs_1]
WARNING: [Vivado 12-818] No files matched 'xdc/Zybo-Z7-Master.xdc' - set_property -name "target_constrs_file" -value "[get_files xdc/Zybo-Z7-Master.xdc]" -objects $obj
WARNING: [Vivado 12-818] No files matched 'xdc/Zybo-Z7-Master.xdc' - set_property -name "target_ucf" -value "[get_files xdc/Zybo-Z7-Master.xdc]" -objects $obj
- if {[string equal [get_filesets -quiet sim_1] ""]} {
- create_fileset -simset sim_1
- }
- set obj [get_filesets sim_1]
- set obj [get_filesets sim_1]
- set_property -name "hbs.configure_design_for_hier_access" -value "1" -objects $obj
- set_property -name "top" -value "design_1_wrapper" -objects $obj
- set_property -name "top_lib" -value "xil_defaultlib" -objects $obj
- set obj [get_filesets utils_1]
- set obj [get_filesets utils_1]
- proc cr_bd_design_1 { parentCell } {
- # CHANGE DESIGN NAME HERE
- set design_name design_1
- common::send_gid_msg -ssname BD::TCL -id 2010 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..."
- create_bd_design $design_name
- set bCheckIPsPassed 1
- ##################################################################
- # CHECK IPs
- ##################################################################
- set bCheckIPs 1
- if { $bCheckIPs == 1 } {
- set list_check_ips "\
- xilinx.com:ip:processing_system7:5.5\
- xilinx.com:ip:proc_sys_reset:5.0\
- xilinx.com:ip:xadc_wiz:3.3\
- "
- set list_ips_missing ""
- common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
- foreach ip_vlnv $list_check_ips {
- set ip_obj [get_ipdefs -all $ip_vlnv]
- if { $ip_obj eq "" } {
- lappend list_ips_missing $ip_vlnv
- }
- }
- if { $list_ips_missing ne "" } {
- catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP to the project." }
- set bCheckIPsPassed 0
- }
- }
- if { $bCheckIPsPassed != 1 } {
- common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above."
- return 3
- }
- variable script_folder
- if { $parentCell eq "" } {
- set parentCell [get_bd_cells /]
- }
- # Get object for parentCell
- set parentObj [get_bd_cells $parentCell]
- if { $parentObj == "" } {
- catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
- return
- }
- # Make sure parentObj is hier blk
- set parentType [get_property TYPE $parentObj]
- if { $parentType ne "hier" } {
- catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
- return
- }
- # Save current instance; Restore later
- set oldCurInst [current_bd_instance .]
- # Set parent object as current
- current_bd_instance $parentObj
- # Create interface ports
- set DDR [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR ]
- set FIXED_IO [ create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 FIXED_IO ]
- set Vaux6 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vaux6 ]
- set Vaux7 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vaux7 ]
- set Vaux14 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vaux14 ]
- set Vaux15 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vaux15 ]
- # Create ports
- # Create instance: processing_system7_0, and set properties
- set processing_system7_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0 ]
- set_property -dict [ list \
- CONFIG.PCW_ACT_APU_PERIPHERAL_FREQMHZ {666.666687} \
- CONFIG.PCW_ACT_CAN_PERIPHERAL_FREQMHZ {10.000000} \
- CONFIG.PCW_ACT_DCI_PERIPHERAL_FREQMHZ {10.158730} \
- CONFIG.PCW_ACT_ENET0_PERIPHERAL_FREQMHZ {125.000000} \
- CONFIG.PCW_ACT_ENET1_PERIPHERAL_FREQMHZ {10.000000} \
- CONFIG.PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ {50.000000} \
- CONFIG.PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ {10.000000} \
- CONFIG.PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ {10.000000} \
- CONFIG.PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ {10.000000} \
- CONFIG.PCW_ACT_PCAP_PERIPHERAL_FREQMHZ {200.000000} \
- CONFIG.PCW_ACT_QSPI_PERIPHERAL_FREQMHZ {200.000000} \
- CONFIG.PCW_ACT_SDIO_PERIPHERAL_FREQMHZ {50.000000} \
- CONFIG.PCW_ACT_SMC_PERIPHERAL_FREQMHZ {10.000000} \
- CONFIG.PCW_ACT_SPI_PERIPHERAL_FREQMHZ {10.000000} \
- CONFIG.PCW_ACT_TPIU_PERIPHERAL_FREQMHZ {200.000000} \
- CONFIG.PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ {111.111115} \
- CONFIG.PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ {111.111115} \
- CONFIG.PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ {111.111115} \
- CONFIG.PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ {111.111115} \
- CONFIG.PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ {111.111115} \
- CONFIG.PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ {111.111115} \
- CONFIG.PCW_ACT_UART_PERIPHERAL_FREQMHZ {100.000000} \
- CONFIG.PCW_ACT_WDT_PERIPHERAL_FREQMHZ {111.111115} \
- CONFIG.PCW_APU_CLK_RATIO_ENABLE {6:2:1} \
- CONFIG.PCW_APU_PERIPHERAL_FREQMHZ {667} \
- CONFIG.PCW_ARMPLL_CTRL_FBDIV {40} \
- CONFIG.PCW_CAN_PERIPHERAL_DIVISOR0 {1} \
- CONFIG.PCW_CAN_PERIPHERAL_DIVISOR1 {1} \
- CONFIG.PCW_CLK0_FREQ {50000000} \
- CONFIG.PCW_CLK1_FREQ {10000000} \
- CONFIG.PCW_CLK2_FREQ {10000000} \
- CONFIG.PCW_CLK3_FREQ {10000000} \
- CONFIG.PCW_CPU_CPU_6X4X_MAX_RANGE {667} \
- CONFIG.PCW_CPU_CPU_PLL_FREQMHZ {1333.333} \
- CONFIG.PCW_CPU_PERIPHERAL_CLKSRC {ARM PLL} \
- CONFIG.PCW_CPU_PERIPHERAL_DIVISOR0 {2} \
- CONFIG.PCW_CRYSTAL_PERIPHERAL_FREQMHZ {33.333333} \
- CONFIG.PCW_DCI_PERIPHERAL_CLKSRC {DDR PLL} \
- CONFIG.PCW_DCI_PERIPHERAL_DIVISOR0 {15} \
- CONFIG.PCW_DCI_PERIPHERAL_DIVISOR1 {7} \
- CONFIG.PCW_DCI_PERIPHERAL_FREQMHZ {10.159} \
- CONFIG.PCW_DDRPLL_CTRL_FBDIV {32} \
- CONFIG.PCW_DDR_DDR_PLL_FREQMHZ {1066.667} \
- CONFIG.PCW_DDR_HPRLPR_QUEUE_PARTITION {HPR/LPR} \
- CONFIG.PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL {15} \
- CONFIG.PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL {2} \
- CONFIG.PCW_DDR_PERIPHERAL_CLKSRC {DDR PLL} \
- CONFIG.PCW_DDR_PERIPHERAL_DIVISOR0 {2} \
- CONFIG.PCW_DDR_PORT0_HPR_ENABLE {0} \
- CONFIG.PCW_DDR_PORT1_HPR_ENABLE {0} \
- CONFIG.PCW_DDR_PORT2_HPR_ENABLE {0} \
- CONFIG.PCW_DDR_PORT3_HPR_ENABLE {0} \
- CONFIG.PCW_DDR_RAM_HIGHADDR {0x3FFFFFFF} \
- CONFIG.PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL {2} \
- CONFIG.PCW_ENET0_ENET0_IO {MIO 16 .. 27} \
- CONFIG.PCW_ENET0_GRP_MDIO_ENABLE {1} \
- CONFIG.PCW_ENET0_GRP_MDIO_IO {MIO 52 .. 53} \
- CONFIG.PCW_ENET0_PERIPHERAL_CLKSRC {IO PLL} \
- CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR0 {8} \
- CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR1 {1} \
- CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {1} \
- CONFIG.PCW_ENET0_PERIPHERAL_FREQMHZ {1000 Mbps} \
- CONFIG.PCW_ENET0_RESET_ENABLE {0} \
- CONFIG.PCW_ENET1_GRP_MDIO_ENABLE {0} \
- CONFIG.PCW_ENET1_PERIPHERAL_CLKSRC {IO PLL} \
- CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR0 {1} \
- CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR1 {1} \
- CONFIG.PCW_ENET1_PERIPHERAL_ENABLE {0} \
- CONFIG.PCW_ENET1_PERIPHERAL_FREQMHZ {1000 Mbps} \
- CONFIG.PCW_ENET1_RESET_ENABLE {0} \
- CONFIG.PCW_ENET_RESET_ENABLE {1} \
- CONFIG.PCW_ENET_RESET_POLARITY {Active Low} \
- CONFIG.PCW_ENET_RESET_SELECT {Share reset pin} \
- CONFIG.PCW_EN_4K_TIMER {0} \
- CONFIG.PCW_EN_ENET0 {1} \
- CONFIG.PCW_EN_GPIO {1} \
- CONFIG.PCW_EN_QSPI {1} \
- CONFIG.PCW_EN_SDIO0 {1} \
- CONFIG.PCW_EN_UART1 {1} \
- CONFIG.PCW_EN_USB0 {0} \
- CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR0 {5} \
- CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR1 {4} \
- CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR0 {1} \
- CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR1 {1} \
- CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR0 {1} \
- CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR1 {1} \
- CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR0 {1} \
- CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR1 {1} \
- CONFIG.PCW_FPGA_FCLK0_ENABLE {1} \
- CONFIG.PCW_FPGA_FCLK1_ENABLE {0} \
- CONFIG.PCW_FPGA_FCLK2_ENABLE {0} \
- CONFIG.PCW_FPGA_FCLK3_ENABLE {0} \
- CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1} \
- CONFIG.PCW_GPIO_MIO_GPIO_IO {MIO} \
- CONFIG.PCW_GPIO_PERIPHERAL_ENABLE {0} \
- CONFIG.PCW_I2C0_RESET_ENABLE {0} \
- CONFIG.PCW_I2C1_RESET_ENABLE {0} \
- CONFIG.PCW_I2C_PERIPHERAL_FREQMHZ {25} \
- CONFIG.PCW_I2C_RESET_ENABLE {1} \
- CONFIG.PCW_IOPLL_CTRL_FBDIV {30} \
- CONFIG.PCW_IO_IO_PLL_FREQMHZ {1000.000} \
- CONFIG.PCW_IRQ_F2P_MODE {DIRECT} \
- CONFIG.PCW_MIO_0_DIRECTION {inout} \
- CONFIG.PCW_MIO_0_IOTYPE {LVCMOS 3.3V} \
- CONFIG.PCW_MIO_0_PULLUP {enabled} \
- CONFIG.PCW_MIO_0_SLEW {slow} \
- CONFIG.PCW_MIO_10_DIRECTION {inout} \
- CONFIG.PCW_MIO_10_IOTYPE {LVCMOS 3.3V} \
- CONFIG.PCW_MIO_10_PULLUP {enabled} \
- CONFIG.PCW_MIO_10_SLEW {slow} \
- CONFIG.PCW_MIO_11_DIRECTION {inout} \
- CONFIG.PCW_MIO_11_IOTYPE {LVCMOS 3.3V} \
- CONFIG.PCW_MIO_11_PULLUP {enabled} \
- CONFIG.PCW_MIO_11_SLEW {slow} \
- CONFIG.PCW_MIO_12_DIRECTION {inout} \
- CONFIG.PCW_MIO_12_IOTYPE {LVCMOS 3.3V} \
- CONFIG.PCW_MIO_12_PULLUP {enabled} \
- CONFIG.PCW_MIO_12_SLEW {slow} \
- CONFIG.PCW_MIO_13_DIRECTION {inout} \
- CONFIG.PCW_MIO_13_IOTYPE {LVCMOS 3.3V} \
- CONFIG.PCW_MIO_13_PULLUP {enabled} \
- CONFIG.PCW_MIO_13_SLEW {slow} \
- CONFIG.PCW_MIO_14_DIRECTION {inout} \
- CONFIG.PCW_MIO_14_IOTYPE {LVCMOS 3.3V} \
- CONFIG.PCW_MIO_14_PULLUP {enabled} \
- CONFIG.PCW_MIO_14_SLEW {slow} \
- CONFIG.PCW_MIO_15_DIRECTION {inout} \
- CONFIG.PCW_MIO_15_IOTYPE {LVCMOS 3.3V} \
- CONFIG.PCW_MIO_15_PULLUP {enabled} \
- CONFIG.PCW_MIO_15_SLEW {slow} \
- CONFIG.PCW_MIO_16_DIRECTION {out} \
- CONFIG.PCW_MIO_16_IOTYPE {LVCMOS 1.8V} \
- CONFIG.PCW_MIO_16_PULLUP {enabled} \
- CONFIG.PCW_MIO_16_SLEW {fast} \
- CONFIG.PCW_MIO_17_DIRECTION {out} \
- CONFIG.PCW_MIO_17_IOTYPE {LVCMOS 1.8V} \
- CONFIG.PCW_MIO_17_PULLUP {enabled} \
- CONFIG.PCW_MIO_17_SLEW {fast} \
- CONFIG.PCW_MIO_18_DIRECTION {out} \
- CONFIG.PCW_MIO_18_IOTYPE {LVCMOS 1.8V} \
- CONFIG.PCW_MIO_18_PULLUP {enabled} \
- CONFIG.PCW_MIO_18_SLEW {fast} \
- CONFIG.PCW_MIO_19_DIRECTION {out} \
- CONFIG.PCW_MIO_19_IOTYPE {LVCMOS 1.8V} \
- CONFIG.PCW_MIO_19_PULLUP {enabled} \
- CONFIG.PCW_MIO_19_SLEW {fast} \
- CONFIG.PCW_MIO_1_DIRECTION {out} \
- CONFIG.PCW_MIO_1_IOTYPE {LVCMOS 3.3V} \
- CONFIG.PCW_MIO_1_PULLUP {enabled} \
- CONFIG.PCW_MIO_1_SLEW {slow} \
- CONFIG.PCW_MIO_20_DIRECTION {out} \
- CONFIG.PCW_MIO_20_IOTYPE {LVCMOS 1.8V} \
- CONFIG.PCW_MIO_20_PULLUP {enabled} \
- CONFIG.PCW_MIO_20_SLEW {fast} \
- CONFIG.PCW_MIO_21_DIRECTION {out} \
- CONFIG.PCW_MIO_21_IOTYPE {LVCMOS 1.8V} \
- CONFIG.PCW_MIO_21_PULLUP {enabled} \
- CONFIG.PCW_MIO_21_SLEW {fast} \
- CONFIG.PCW_MIO_22_DIRECTION {in} \
- CONFIG.PCW_MIO_22_IOTYPE {LVCMOS 1.8V} \
- CONFIG.PCW_MIO_22_PULLUP {enabled} \
- CONFIG.PCW_MIO_22_SLEW {fast} \
- CONFIG.PCW_MIO_23_DIRECTION {in} \
- CONFIG.PCW_MIO_23_IOTYPE {LVCMOS 1.8V} \
- CONFIG.PCW_MIO_23_PULLUP {enabled} \
- CONFIG.PCW_MIO_23_SLEW {fast} \
- CONFIG.PCW_MIO_24_DIRECTION {in} \
- CONFIG.PCW_MIO_24_IOTYPE {LVCMOS 1.8V} \
- CONFIG.PCW_MIO_24_PULLUP {enabled} \
- CONFIG.PCW_MIO_24_SLEW {fast} \
- CONFIG.PCW_MIO_25_DIRECTION {in} \
- CONFIG.PCW_MIO_25_IOTYPE {LVCMOS 1.8V} \
- CONFIG.PCW_MIO_25_PULLUP {enabled} \
- CONFIG.PCW_MIO_25_SLEW {fast} \
- CONFIG.PCW_MIO_26_DIRECTION {in} \
- CONFIG.PCW_MIO_26_IOTYPE {LVCMOS 1.8V} \
- CONFIG.PCW_MIO_26_PULLUP {enabled} \
- CONFIG.PCW_MIO_26_SLEW {fast} \
- CONFIG.PCW_MIO_27_DIRECTION {in} \
- CONFIG.PCW_MIO_27_IOTYPE {LVCMOS 1.8V} \
- CONFIG.PCW_MIO_27_PULLUP {enabled} \
- CONFIG.PCW_MIO_27_SLEW {fast} \
- CONFIG.PCW_MIO_28_DIRECTION {inout} \
- CONFIG.PCW_MIO_28_IOTYPE {LVCMOS 1.8V} \
- CONFIG.PCW_MIO_28_PULLUP {enabled} \
- CONFIG.PCW_MIO_28_SLEW {fast} \
- CONFIG.PCW_MIO_29_DIRECTION {in} \
- CONFIG.PCW_MIO_29_IOTYPE {LVCMOS 1.8V} \
- CONFIG.PCW_MIO_29_PULLUP {enabled} \
- CONFIG.PCW_MIO_29_SLEW {fast} \
- CONFIG.PCW_MIO_2_DIRECTION {inout} \
- CONFIG.PCW_MIO_2_IOTYPE {LVCMOS 3.3V} \
- CONFIG.PCW_MIO_2_PULLUP {disabled} \
- CONFIG.PCW_MIO_2_SLEW {slow} \
- CONFIG.PCW_MIO_30_DIRECTION {out} \
- CONFIG.PCW_MIO_30_IOTYPE {LVCMOS 1.8V} \
- CONFIG.PCW_MIO_30_PULLUP {enabled} \
- CONFIG.PCW_MIO_30_SLEW {fast} \
- CONFIG.PCW_MIO_31_DIRECTION {in} \
- CONFIG.PCW_MIO_31_IOTYPE {LVCMOS 1.8V} \
- CONFIG.PCW_MIO_31_PULLUP {enabled} \
- CONFIG.PCW_MIO_31_SLEW {fast} \
- CONFIG.PCW_MIO_32_DIRECTION {inout} \
- CONFIG.PCW_MIO_32_IOTYPE {LVCMOS 1.8V} \
- CONFIG.PCW_MIO_32_PULLUP {enabled} \
- CONFIG.PCW_MIO_32_SLEW {fast} \
- CONFIG.PCW_MIO_33_DIRECTION {inout} \
- CONFIG.PCW_MIO_33_IOTYPE {LVCMOS 1.8V} \
- CONFIG.PCW_MIO_33_PULLUP {enabled} \
- CONFIG.PCW_MIO_33_SLEW {fast} \
- CONFIG.PCW_MIO_34_DIRECTION {inout} \
- CONFIG.PCW_MIO_34_IOTYPE {LVCMOS 1.8V} \
- CONFIG.PCW_MIO_34_PULLUP {enabled} \
- CONFIG.PCW_MIO_34_SLEW {fast} \
- CONFIG.PCW_MIO_35_DIRECTION {inout} \
- CONFIG.PCW_MIO_35_IOTYPE {LVCMOS 1.8V} \
- CONFIG.PCW_MIO_35_PULLUP {enabled} \
- CONFIG.PCW_MIO_35_SLEW {fast} \
- CONFIG.PCW_MIO_36_DIRECTION {in} \
- CONFIG.PCW_MIO_36_IOTYPE {LVCMOS 1.8V} \
- CONFIG.PCW_MIO_36_PULLUP {enabled} \
- CONFIG.PCW_MIO_36_SLEW {fast} \
- CONFIG.PCW_MIO_37_DIRECTION {inout} \
- CONFIG.PCW_MIO_37_IOTYPE {LVCMOS 1.8V} \
- CONFIG.PCW_MIO_37_PULLUP {enabled} \
- CONFIG.PCW_MIO_37_SLEW {fast} \
- CONFIG.PCW_MIO_38_DIRECTION {inout} \
- CONFIG.PCW_MIO_38_IOTYPE {LVCMOS 1.8V} \
- CONFIG.PCW_MIO_38_PULLUP {enabled} \
- CONFIG.PCW_MIO_38_SLEW {fast} \
- CONFIG.PCW_MIO_39_DIRECTION {inout} \
- CONFIG.PCW_MIO_39_IOTYPE {LVCMOS 1.8V} \
- CONFIG.PCW_MIO_39_PULLUP {enabled} \
- CONFIG.PCW_MIO_39_SLEW {fast} \
- CONFIG.PCW_MIO_3_DIRECTION {inout} \
- CONFIG.PCW_MIO_3_IOTYPE {LVCMOS 3.3V} \
- CONFIG.PCW_MIO_3_PULLUP {disabled} \
- CONFIG.PCW_MIO_3_SLEW {slow} \
- CONFIG.PCW_MIO_40_DIRECTION {inout} \
- CONFIG.PCW_MIO_40_IOTYPE {LVCMOS 1.8V} \
- CONFIG.PCW_MIO_40_PULLUP {enabled} \
- CONFIG.PCW_MIO_40_SLEW {slow} \
- CONFIG.PCW_MIO_41_DIRECTION {inout} \
- CONFIG.PCW_MIO_41_IOTYPE {LVCMOS 1.8V} \
- CONFIG.PCW_MIO_41_PULLUP {enabled} \
- CONFIG.PCW_MIO_41_SLEW {slow} \
- CONFIG.PCW_MIO_42_DIRECTION {inout} \
- CONFIG.PCW_MIO_42_IOTYPE {LVCMOS 1.8V} \
- CONFIG.PCW_MIO_42_PULLUP {enabled} \
- CONFIG.PCW_MIO_42_SLEW {slow} \
- CONFIG.PCW_MIO_43_DIRECTION {inout} \
- CONFIG.PCW_MIO_43_IOTYPE {LVCMOS 1.8V} \
- CONFIG.PCW_MIO_43_PULLUP {enabled} \
- CONFIG.PCW_MIO_43_SLEW {slow} \
- CONFIG.PCW_MIO_44_DIRECTION {inout} \
- CONFIG.PCW_MIO_44_IOTYPE {LVCMOS 1.8V} \
- CONFIG.PCW_MIO_44_PULLUP {enabled} \
- CONFIG.PCW_MIO_44_SLEW {slow} \
- CONFIG.PCW_MIO_45_DIRECTION {inout} \
- CONFIG.PCW_MIO_45_IOTYPE {LVCMOS 1.8V} \
- CONFIG.PCW_MIO_45_PULLUP {enabled} \
- CONFIG.PCW_MIO_45_SLEW {slow} \
- CONFIG.PCW_MIO_46_DIRECTION {out} \
- CONFIG.PCW_MIO_46_IOTYPE {LVCMOS 1.8V} \
- CONFIG.PCW_MIO_46_PULLUP {enabled} \
- CONFIG.PCW_MIO_46_SLEW {slow} \
- CONFIG.PCW_MIO_47_DIRECTION {in} \
- CONFIG.PCW_MIO_47_IOTYPE {LVCMOS 1.8V} \
- CONFIG.PCW_MIO_47_PULLUP {enabled} \
- CONFIG.PCW_MIO_47_SLEW {slow} \
- CONFIG.PCW_MIO_48_DIRECTION {out} \
- CONFIG.PCW_MIO_48_IOTYPE {LVCMOS 1.8V} \
- CONFIG.PCW_MIO_48_PULLUP {enabled} \
- CONFIG.PCW_MIO_48_SLEW {slow} \
- CONFIG.PCW_MIO_49_DIRECTION {in} \
- CONFIG.PCW_MIO_49_IOTYPE {LVCMOS 1.8V} \
- CONFIG.PCW_MIO_49_PULLUP {enabled} \
- CONFIG.PCW_MIO_49_SLEW {slow} \
- CONFIG.PCW_MIO_4_DIRECTION {inout} \
- CONFIG.PCW_MIO_4_IOTYPE {LVCMOS 3.3V} \
- CONFIG.PCW_MIO_4_PULLUP {disabled} \
- CONFIG.PCW_MIO_4_SLEW {slow} \
- CONFIG.PCW_MIO_50_DIRECTION {inout} \
- CONFIG.PCW_MIO_50_IOTYPE {LVCMOS 1.8V} \
- CONFIG.PCW_MIO_50_PULLUP {enabled} \
- CONFIG.PCW_MIO_50_SLEW {slow} \
- CONFIG.PCW_MIO_51_DIRECTION {inout} \
- CONFIG.PCW_MIO_51_IOTYPE {LVCMOS 1.8V} \
- CONFIG.PCW_MIO_51_PULLUP {enabled} \
- CONFIG.PCW_MIO_51_SLEW {slow} \
- CONFIG.PCW_MIO_52_DIRECTION {out} \
- CONFIG.PCW_MIO_52_IOTYPE {LVCMOS 1.8V} \
- CONFIG.PCW_MIO_52_PULLUP {enabled} \
- CONFIG.PCW_MIO_52_SLEW {slow} \
- CONFIG.PCW_MIO_53_DIRECTION {inout} \
- CONFIG.PCW_MIO_53_IOTYPE {LVCMOS 1.8V} \
- CONFIG.PCW_MIO_53_PULLUP {enabled} \
- CONFIG.PCW_MIO_53_SLEW {slow} \
- CONFIG.PCW_MIO_5_DIRECTION {inout} \
- CONFIG.PCW_MIO_5_IOTYPE {LVCMOS 3.3V} \
- CONFIG.PCW_MIO_5_PULLUP {disabled} \
- CONFIG.PCW_MIO_5_SLEW {slow} \
- CONFIG.PCW_MIO_6_DIRECTION {out} \
- CONFIG.PCW_MIO_6_IOTYPE {LVCMOS 3.3V} \
- CONFIG.PCW_MIO_6_PULLUP {disabled} \
- CONFIG.PCW_MIO_6_SLEW {slow} \
- CONFIG.PCW_MIO_7_DIRECTION {out} \
- CONFIG.PCW_MIO_7_IOTYPE {LVCMOS 3.3V} \
- CONFIG.PCW_MIO_7_PULLUP {disabled} \
- CONFIG.PCW_MIO_7_SLEW {slow} \
- CONFIG.PCW_MIO_8_DIRECTION {out} \
- CONFIG.PCW_MIO_8_IOTYPE {LVCMOS 3.3V} \
- CONFIG.PCW_MIO_8_PULLUP {disabled} \
- CONFIG.PCW_MIO_8_SLEW {slow} \
- CONFIG.PCW_MIO_9_DIRECTION {inout} \
- CONFIG.PCW_MIO_9_IOTYPE {LVCMOS 3.3V} \
- CONFIG.PCW_MIO_9_PULLUP {enabled} \
- CONFIG.PCW_MIO_9_SLEW {slow} \
- CONFIG.PCW_MIO_TREE_PERIPHERALS { \
- 0#Enet 0 \
- 0#Enet 0 \
- 0#Enet 0 \
- 0#Enet 0 \
- 0#Enet 0 \
- 0#Enet 0 \
- 0#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#SD 0#SD \
- 0#GPIO#SD 0#UART \
- 0#SD 0#SD \
- 0#SD 0#SD \
- 1#UART 1#GPIO#GPIO#Enet \
- Flash#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#Enet 0#Enet \
- Flash#GPIO#Quad SPI \
- Flash#Quad SPI \
- Flash#Quad SPI \
- Flash#Quad SPI \
- Flash#Quad SPI \
- Flash#Quad SPI \
- GPIO#Quad SPI \
- } \
- CONFIG.PCW_MIO_TREE_SIGNALS {gpio0#qspi0_ss_b#qspi0_io0#qspi0_io1#qspi0_io2#qspi0_io3/HOLD_B#qspi0_sclk#gpio7#qspi_fbclk#gpio9#gpio10#gpio11#gpio12#gpio13#gpio14#gpio15#tx_clk#txd0#txd1#txd2#txd3#tx_ctl#rx_clk#rxd0#rxd1#rxd2#rxd3#rx_ctl#gpio28#gpio29#gpio30#gpio31#gpio32#gpio33#gpio34#gpio35#gpio36#gpio37#gpio38#gpio39#clk#cmd#data0#data1#data2#data3#gpio46#cd#tx#rx#gpio50#gpio51#mdc#mdio} \
- CONFIG.PCW_NAND_GRP_D8_ENABLE {0} \
- CONFIG.PCW_NAND_PERIPHERAL_ENABLE {0} \
- CONFIG.PCW_NOR_GRP_A25_ENABLE {0} \
- CONFIG.PCW_NOR_GRP_CS0_ENABLE {0} \
- CONFIG.PCW_NOR_GRP_CS1_ENABLE {0} \
- CONFIG.PCW_NOR_GRP_SRAM_CS0_ENABLE {0} \
- CONFIG.PCW_NOR_GRP_SRAM_CS1_ENABLE {0} \
- CONFIG.PCW_NOR_GRP_SRAM_INT_ENABLE {0} \
- CONFIG.PCW_NOR_PERIPHERAL_ENABLE {0} \
- CONFIG.PCW_OVERRIDE_BASIC_CLOCK {0} \
- CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY0 {0.221} \
- CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY1 {0.222} \
- CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY2 {0.217} \
- CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY3 {0.244} \
- CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_0 {-0.050} \
- CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_1 {-0.044} \
- CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_2 {-0.035} \
- CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_3 {-0.100} \
- CONFIG.PCW_PCAP_PERIPHERAL_CLKSRC {IO PLL} \
- CONFIG.PCW_PCAP_PERIPHERAL_DIVISOR0 {5} \
- CONFIG.PCW_PCAP_PERIPHERAL_FREQMHZ {200} \
- CONFIG.PCW_PJTAG_PERIPHERAL_ENABLE {0} \
- CONFIG.PCW_PLL_BYPASSMODE_ENABLE {0} \
- CONFIG.PCW_PRESET_BANK0_VOLTAGE {LVCMOS 3.3V} \
- CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 1.8V} \
- CONFIG.PCW_QSPI_GRP_FBCLK_ENABLE {1} \
- CONFIG.PCW_QSPI_GRP_FBCLK_IO {MIO 8} \
- CONFIG.PCW_QSPI_GRP_IO1_ENABLE {0} \
- CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE {1} \
- CONFIG.PCW_QSPI_GRP_SINGLE_SS_IO {MIO 1 .. 6} \
- CONFIG.PCW_QSPI_GRP_SS1_ENABLE {0} \
- CONFIG.PCW_QSPI_INTERNAL_HIGHADDRESS {0xFCFFFFFF} \
- CONFIG.PCW_QSPI_PERIPHERAL_CLKSRC {IO PLL} \
- CONFIG.PCW_QSPI_PERIPHERAL_DIVISOR0 {5} \
- CONFIG.PCW_QSPI_PERIPHERAL_ENABLE {1} \
- CONFIG.PCW_QSPI_PERIPHERAL_FREQMHZ {200} \
- CONFIG.PCW_QSPI_QSPI_IO {MIO 1 .. 6} \
- CONFIG.PCW_SD0_GRP_CD_ENABLE {1} \
- CONFIG.PCW_SD0_GRP_CD_IO {MIO 47} \
- CONFIG.PCW_SD0_GRP_POW_ENABLE {0} \
- CONFIG.PCW_SD0_GRP_WP_ENABLE {0} \
- CONFIG.PCW_SD0_PERIPHERAL_ENABLE {1} \
- CONFIG.PCW_SD0_SD0_IO {MIO 40 .. 45} \
- CONFIG.PCW_SDIO_PERIPHERAL_CLKSRC {IO PLL} \
- CONFIG.PCW_SDIO_PERIPHERAL_DIVISOR0 {20} \
- CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ {50} \
- CONFIG.PCW_SDIO_PERIPHERAL_VALID {1} \
- CONFIG.PCW_SINGLE_QSPI_DATA_MODE {x4} \
- CONFIG.PCW_SMC_PERIPHERAL_CLKSRC {IO PLL} \
- CONFIG.PCW_SMC_PERIPHERAL_DIVISOR0 {1} \
- CONFIG.PCW_SMC_PERIPHERAL_FREQMHZ {100} \
- CONFIG.PCW_SPI_PERIPHERAL_DIVISOR0 {1} \
- CONFIG.PCW_TPIU_PERIPHERAL_CLKSRC {External} \
- CONFIG.PCW_TPIU_PERIPHERAL_DIVISOR0 {1} \
- CONFIG.PCW_TPIU_PERIPHERAL_FREQMHZ {200} \
- CONFIG.PCW_UART0_GRP_FULL_ENABLE {0} \
- CONFIG.PCW_UART0_PERIPHERAL_ENABLE {0} \
- CONFIG.PCW_UART1_BAUD_RATE {115200} \
- CONFIG.PCW_UART1_GRP_FULL_ENABLE {0} \
- CONFIG.PCW_UART1_PERIPHERAL_ENABLE {1} \
- CONFIG.PCW_UART1_UART1_IO {MIO 48 .. 49} \
- CONFIG.PCW_UART_PERIPHERAL_CLKSRC {IO PLL} \
- CONFIG.PCW_UART_PERIPHERAL_DIVISOR0 {10} \
- CONFIG.PCW_UART_PERIPHERAL_FREQMHZ {100} \
- CONFIG.PCW_UART_PERIPHERAL_VALID {1} \
- CONFIG.PCW_UIPARAM_ACT_DDR_FREQ_MHZ {533.333374} \
- CONFIG.PCW_UIPARAM_DDR_ADV_ENABLE {0} \
- CONFIG.PCW_UIPARAM_DDR_AL {0} \
- CONFIG.PCW_UIPARAM_DDR_BANK_ADDR_COUNT {3} \
- CONFIG.PCW_UIPARAM_DDR_BL {8} \
- CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0 {0.221} \
- CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1 {0.222} \
- CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2 {0.217} \
- CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3 {0.244} \
- CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH {32 Bit} \
- CONFIG.PCW_UIPARAM_DDR_CL {7} \
- CONFIG.PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM {18.8} \
- CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH {80.4535} \
- CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY {160} \
- CONFIG.PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM {18.8} \
- CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH {80.4535} \
- CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY {160} \
- CONFIG.PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM {18.8} \
- CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH {80.4535} \
- CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY {160} \
- CONFIG.PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM {18.8} \
- CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH {80.4535} \
- CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY {160} \
- CONFIG.PCW_UIPARAM_DDR_CLOCK_STOP_EN {0} \
- CONFIG.PCW_UIPARAM_DDR_COL_ADDR_COUNT {10} \
- CONFIG.PCW_UIPARAM_DDR_CWL {6} \
- CONFIG.PCW_UIPARAM_DDR_DEVICE_CAPACITY {4096 MBits} \
- CONFIG.PCW_UIPARAM_DDR_DQS_0_LENGTH_MM {22.8} \
- CONFIG.PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH {105.056} \
- CONFIG.PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY {160} \
- CONFIG.PCW_UIPARAM_DDR_DQS_1_LENGTH_MM {27.9} \
- CONFIG.PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH {66.904} \
- CONFIG.PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY {160} \
- CONFIG.PCW_UIPARAM_DDR_DQS_2_LENGTH_MM {22.9} \
- CONFIG.PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH {89.1715} \
- CONFIG.PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY {160} \
- CONFIG.PCW_UIPARAM_DDR_DQS_3_LENGTH_MM {29.4} \
- CONFIG.PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH {113.63} \
- CONFIG.PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY {160} \
- CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 {-0.050} \
- CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 {-0.044} \
- CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 {-0.035} \
- CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 {-0.100} \
- CONFIG.PCW_UIPARAM_DDR_DQ_0_LENGTH_MM {22.8} \
- CONFIG.PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH {98.503} \
- CONFIG.PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY {160} \
- CONFIG.PCW_UIPARAM_DDR_DQ_1_LENGTH_MM {27.9} \
- CONFIG.PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH {68.5855} \
- CONFIG.PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY {160} \
- CONFIG.PCW_UIPARAM_DDR_DQ_2_LENGTH_MM {22.9} \
- CONFIG.PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH {90.295} \
- CONFIG.PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY {160} \
- CONFIG.PCW_UIPARAM_DDR_DQ_3_LENGTH_MM {29.4} \
- CONFIG.PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH {103.977} \
- CONFIG.PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY {160} \
- CONFIG.PCW_UIPARAM_DDR_DRAM_WIDTH {16 Bits} \
- CONFIG.PCW_UIPARAM_DDR_ECC {Disabled} \
- CONFIG.PCW_UIPARAM_DDR_ENABLE {1} \
- CONFIG.PCW_UIPARAM_DDR_FREQ_MHZ {533.333333} \
- CONFIG.PCW_UIPARAM_DDR_HIGH_TEMP {Normal (0-85)} \
- CONFIG.PCW_UIPARAM_DDR_MEMORY_TYPE {DDR 3 (Low Voltage)} \
- CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41K256M16 RE-125} \
- CONFIG.PCW_UIPARAM_DDR_ROW_ADDR_COUNT {15} \
- CONFIG.PCW_UIPARAM_DDR_SPEED_BIN {DDR3_1066F} \
- CONFIG.PCW_UIPARAM_DDR_TRAIN_DATA_EYE {1} \
- CONFIG.PCW_UIPARAM_DDR_TRAIN_READ_GATE {1} \
- CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL {1} \
- CONFIG.PCW_UIPARAM_DDR_T_FAW {40.0} \
- CONFIG.PCW_UIPARAM_DDR_T_RAS_MIN {35.0} \
- CONFIG.PCW_UIPARAM_DDR_T_RC {48.75} \
- CONFIG.PCW_UIPARAM_DDR_T_RCD {7} \
- CONFIG.PCW_UIPARAM_DDR_T_RP {7} \
- CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF {0} \
- CONFIG.PCW_USB0_PERIPHERAL_ENABLE {0} \
- CONFIG.PCW_USB0_PERIPHERAL_FREQMHZ {60} \
- CONFIG.PCW_USB0_RESET_ENABLE {1} \
- CONFIG.PCW_USB0_RESET_IO {MIO 46} \
- CONFIG.PCW_USB0_USB0_IO {<Select>} \
- CONFIG.PCW_USB1_RESET_ENABLE {0} \
- CONFIG.PCW_USB_RESET_ENABLE {1} \
- CONFIG.PCW_USB_RESET_POLARITY {Active Low} \
- CONFIG.PCW_USB_RESET_SELECT {<Select>} \
- CONFIG.PCW_USE_AXI_NONSECURE {0} \
- CONFIG.PCW_USE_CROSS_TRIGGER {0} \
- CONFIG.PCW_USE_M_AXI_GP0 {1} \
- ] $processing_system7_0
- # Create instance: ps7_0_axi_periph, and set properties
- set ps7_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 ps7_0_axi_periph ]
- set_property -dict [ list \
- CONFIG.NUM_MI {1} \
- ] $ps7_0_axi_periph
- # Create instance: rst_ps7_0_50M, and set properties
- set rst_ps7_0_50M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_ps7_0_50M ]
- # Create instance: xadc_wiz_0, and set properties
- set xadc_wiz_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xadc_wiz:3.3 xadc_wiz_0 ]
- set_property -dict [ list \
- CONFIG.ADC_OFFSET_AND_GAIN_CALIBRATION {false} \
- CONFIG.CHANNEL_ENABLE_VAUXP14_VAUXN14 {true} \
- CONFIG.CHANNEL_ENABLE_VAUXP15_VAUXN15 {true} \
- CONFIG.CHANNEL_ENABLE_VAUXP6_VAUXN6 {true} \
- CONFIG.CHANNEL_ENABLE_VAUXP7_VAUXN7 {true} \
- CONFIG.CHANNEL_ENABLE_VP_VN {false} \
- CONFIG.ENABLE_CALIBRATION_AVERAGING {false} \
- CONFIG.ENABLE_VCCDDRO_ALARM {false} \
- CONFIG.ENABLE_VCCPAUX_ALARM {false} \
- CONFIG.ENABLE_VCCPINT_ALARM {false} \
- CONFIG.EXTERNAL_MUX_CHANNEL {VP_VN} \
- CONFIG.OT_ALARM {false} \
- CONFIG.SENSOR_OFFSET_AND_GAIN_CALIBRATION {false} \
- CONFIG.SEQUENCER_MODE {Continuous} \
- CONFIG.SINGLE_CHANNEL_SELECTION {TEMPERATURE} \
- CONFIG.USER_TEMP_ALARM {false} \
- CONFIG.VCCAUX_ALARM {false} \
- CONFIG.VCCINT_ALARM {false} \
- CONFIG.XADC_STARUP_SELECTION {channel_sequencer} \
- ] $xadc_wiz_0
- # Create interface connections
- connect_bd_intf_net -intf_net Vaux14_1 [get_bd_intf_ports Vaux14] [get_bd_intf_pins xadc_wiz_0/Vaux14]
- connect_bd_intf_net -intf_net Vaux15_1 [get_bd_intf_ports Vaux15] [get_bd_intf_pins xadc_wiz_0/Vaux15]
- connect_bd_intf_net -intf_net Vaux6_1 [get_bd_intf_ports Vaux6] [get_bd_intf_pins xadc_wiz_0/Vaux6]
- connect_bd_intf_net -intf_net Vaux7_1 [get_bd_intf_ports Vaux7] [get_bd_intf_pins xadc_wiz_0/Vaux7]
- connect_bd_intf_net -intf_net processing_system7_0_DDR [get_bd_intf_ports DDR] [get_bd_intf_pins processing_system7_0/DDR]
- connect_bd_intf_net -intf_net processing_system7_0_FIXED_IO [get_bd_intf_ports FIXED_IO] [get_bd_intf_pins processing_system7_0/FIXED_IO]
- connect_bd_intf_net -intf_net processing_system7_0_M_AXI_GP0 [get_bd_intf_pins processing_system7_0/M_AXI_GP0] [get_bd_intf_pins ps7_0_axi_periph/S00_AXI]
- connect_bd_intf_net -intf_net ps7_0_axi_periph_M00_AXI [get_bd_intf_pins ps7_0_axi_periph/M00_AXI] [get_bd_intf_pins xadc_wiz_0/s_axi_lite]
- # Create port connections
- connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins ps7_0_axi_periph/ACLK] [get_bd_pins ps7_0_axi_periph/M00_ACLK] [get_bd_pins ps7_0_axi_periph/S00_ACLK] [get_bd_pins rst_ps7_0_50M/slowest_sync_clk] [get_bd_pins xadc_wiz_0/s_axi_aclk]
- connect_bd_net -net processing_system7_0_FCLK_RESET0_N [get_bd_pins processing_system7_0/FCLK_RESET0_N] [get_bd_pins rst_ps7_0_50M/ext_reset_in]
- connect_bd_net -net rst_ps7_0_50M_peripheral_aresetn [get_bd_pins ps7_0_axi_periph/ARESETN] [get_bd_pins ps7_0_axi_periph/M00_ARESETN] [get_bd_pins ps7_0_axi_periph/S00_ARESETN] [get_bd_pins rst_ps7_0_50M/peripheral_aresetn] [get_bd_pins xadc_wiz_0/s_axi_aresetn]
- # Create address segments
- assign_bd_address -offset 0x43C00000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs xadc_wiz_0/s_axi_lite/Reg] -force
- # Perform GUI Layout
- regenerate_bd_layout -layout_string {
- "ActiveEmotionalView":"Default View",
- "Default View_ScaleFactor":"0.951852",
- "Default View_TopLeft":"-139,30",
- "ExpandedHierarchyInLayout":"",
- "guistr":"# # String gsaved with Nlview 7.0r6 2020-01-29 bk=1.5227 VDI=41 GEI=36 GUI=JA:10.0 non-TLS
- # -string -flagsOSRD
- preplace port DDR -pg 1 -lvl 4 -x 1080 -y 60 -defaultsOSRD
- preplace port FIXED_IO -pg 1 -lvl 4 -x 1080 -y 80 -defaultsOSRD
- preplace port Vaux6 -pg 1 -lvl 0 -x -10 -y 210 -defaultsOSRD
- preplace port Vaux7 -pg 1 -lvl 0 -x -10 -y 420 -defaultsOSRD
- preplace port Vaux14 -pg 1 -lvl 0 -x -10 -y 470 -defaultsOSRD
- preplace port Vaux15 -pg 1 -lvl 0 -x -10 -y 490 -defaultsOSRD
- preplace inst processing_system7_0 -pg 1 -lvl 1 -x 230 -y 100 -defaultsOSRD
- preplace inst xadc_wiz_0 -pg 1 -lvl 3 -x 930 -y 410 -defaultsOSRD
- preplace inst ps7_0_axi_periph -pg 1 -lvl 2 -x 610 -y 340 -defaultsOSRD
- preplace inst rst_ps7_0_50M -pg 1 -lvl 1 -x 230 -y 320 -defaultsOSRD
- preplace netloc processing_system7_0_FCLK_CLK0 1 0 3 20 430 440 480 790
- preplace netloc processing_system7_0_FCLK_RESET0_N 1 0 2 30 420 430
- preplace netloc rst_ps7_0_50M_peripheral_aresetn 1 1 2 450 500 800J
- preplace netloc processing_system7_0_DDR 1 1 3 NJ 60 NJ 60 NJ
- preplace netloc processing_system7_0_FIXED_IO 1 1 3 NJ 80 NJ 80 NJ
- preplace netloc processing_system7_0_M_AXI_GP0 1 1 1 450 100n
- preplace netloc ps7_0_axi_periph_M00_AXI 1 2 1 N 340
- preplace netloc Vaux6_1 1 0 3 NJ 210 NJ 210 760J
- preplace netloc Vaux7_1 1 0 3 10J 460 NJ 460 760J
- preplace netloc Vaux14_1 1 0 3 NJ 470 NJ 470 770J
- preplace netloc Vaux15_1 1 0 3 NJ 490 NJ 490 780J
- levelinfo -pg 1 -10 230 610 930 1080
- pagesize -pg 1 -db -bbox -sgen -110 0 1200 540
- "
- }
- # Restore current instance
- current_bd_instance $oldCurInst
- validate_bd_design
- save_bd_design
- close_bd_design $design_name
- }
- cr_bd_design_1 ""
INFO: [BD::TCL 103-2010] Currently there is no design <design_1> in project, so creating one...
Wrote : <C:\aaa\aaa\adc_demo\adc_demo.srcs\sources_1\bd\design_1\design_1.bd>
create_bd_design: Time (s): cpu = 00:00:07 ; elapsed = 00:00:05 . Memory (MB): peak = 1140.660 ; gain = 0.000
INFO: [BD::TCL 103-2011] Checking if the following IPs exist in the project's IP catalog:
xilinx.com:ip:processing_system7:5.5 xilinx.com:ip:proc_sys_reset:5.0 xilinx.com:ip:xadc_wiz:3.3 .
WARNING: [IP_Flow 19-3331] Invalid parameters found in dependency constraints of 'ADDRBLOCK_RANGE.S_AXI_ACP.ACP_QSPI_LINEAR'
WARNING: [IP_Flow 19-3331] Invalid parameters found in dependency constraints of 'ADDRBLOCK_RANGE.S_AXI_ACP.ACP_QSPI_LINEAR'
WARNING: [IP_Flow 19-3553] Error found in parameter dependencies in XGUI files.
ERROR: [IP_Flow 19-3428] Failed to create Customization object design_1_processing_system7_0_0
CRITICAL WARNING: [IP_Flow 19-5622] Failed to create IP instance 'design_1_processing_system7_0_0'. Failed to customize IP instance 'design_1_processing_system7_0_0'. Failed to load customization data
ERROR: [BD 41-1712] Create IP failed with errors
ERROR: [BD 5-7] Error: running create_bd_cell -vlnv xilinx.com:ip:processing_system7:5.5 -type ip -name processing_system7_0 .
ERROR: [Common 17-39] 'create_bd_cell' failed due to earlier errors.
while executing
"create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0 "
(procedure "cr_bd_design_1" line 85)
invoked from within
"cr_bd_design_1 """
(file "zybo7z20_adc_demo.tcl" line 885)
update_compile_order -fileset sources_1
set_property source_mgmt_mode DisplayOnly [current_project]
Replies (7)
RE: Errors when generating .xsa file (adc_demo project) - Added by Shawn Sebastian Pulle (ฌอน) over 1 year ago
Hi Johan,
Thank you for the feedback.
I see one particular message mentioning that the constraint file is not available. Did you go through the process of downloading and copying the constraint files/board files to your vivado installation?
We have mentioned this under step 12 of the prerequisite section of the user guide.
Step 12: Once the installation is finish successfully. Install Digilent's Board Files to add Zybo Z7-20 board to the Vivado design suite
If this is not the first tcl file from a demo you have attempted to run, then it is likely not a board file issue.
Please confirm that the board files are available in the location expected by vivado before we proceed further.
Best Regards,
Shawn
RE: Errors when generating .xsa file (adc_demo project) - Added by Shawn Sebastian Pulle (ฌอน) over 1 year ago
Hi Johan,
It is much more likely that the board part file versions are not compatible.
issued the command: get_board_parts zybo result: digilentinc.com:zybo-z7-10:part0:1.1 digilentinc.com:zybo-z7-20:part0:1.1 digilentinc.com:zybo:part0:1.0 digilentinc.com:zybo:part0:2.0
It looks like you have zybo-z7-20:part0:1.1 installed. During the implementation and testing of the blockset only version 1.0 of these files were available.
There are 2 possible solutions for this.
1) Go to line 135 of the zybo7z20_adc_demo.tcl file and change the version to 1.1. (we have not tested this extensively. So we recommend the second solution instead. Plus you would have to edit every tcl script for other demos this way if you intend to run them.)
2) download and install the older part files (no need to edit the tcl file for this solution)
Please let us know your findings.
Best Regards,
Shawn
RE: Errors when generating .xsa file (adc_demo project) - Added by Johan Henning over 1 year ago
Hello Shawn,
Thanks for helping with this issue. I installed the older board files but now I ran into other errors. Can you have a look into it, please?
This is my directory:
pwd
C:/AimaginProjects/Z7000/adc_demo/hardware_design/vivado_tcl
This is what resides in it:
ls
adc_demo
readme.txt
xdc
zybo7z20_adc_demo.tcl
These are the zybo boards in Vivado:
get_board_parts zy
digilentinc.com:zybo-z7-10:part0:1.1 digilentinc.com:zybo-z7-20:part0:1.0 digilentinc.com:zybo:part0:1.0 digilentinc.com:zybo:part0:2.0
source zybo7z20_adc_demo.tcl
- proc checkRequiredFiles { origin_dir} {
- set status true
- set files [list \
- "xdc/Zybo-Z7-Master.xdc" \
- ]
- foreach ifile $files {
- if { ![file isfile $ifile] } {
- puts " Could not find local file $ifile "
- set status false
- }
- }
- return $status
- }
- set origin_dir "."
- if { [info exists ::origin_dir_loc] } {
- set origin_dir $::origin_dir_loc
- }
- set xil_proj_name "adc_demo"
- if { [info exists ::user_project_name] } {
- set xil_proj_name $::user_project_name
- }
- variable script_file
- set script_file "zybo7z20_adc_demo.tcl"
- proc print_help {} {
- variable script_file
- puts "\nDescription:"
- puts "Recreate a Vivado project from this script. The created project will be"
- puts "functionally equivalent to the original project for which this script was"
- puts "generated. The script contains commands for creating a project, filesets,"
- puts "runs, adding/importing sources and setting properties on various objects.\n"
- puts "Syntax:"
- puts "$script_file"
- puts "$script_file -tclargs \[--origin_dir <path>\]"
- puts "$script_file -tclargs \[--project_name <name>\]"
- puts "$script_file -tclargs \[--help\]\n"
- puts "Usage:"
- puts "Name Description"
- puts "-------------------------------------------------------------------------"
- puts "\[--origin_dir <path>\] Determine source file paths wrt this path. Default"
- puts " origin_dir path value is \".\", otherwise, the value"
- puts " that was set with the \"-paths_relative_to\" switch"
- puts " when this script was generated.\n"
- puts "\[--project_name <name>\] Create project with the specified name. Default"
- puts " name is the name of the project from where this"
- puts " script was generated.\n"
- puts "\[--help\] Print help information for this script"
- puts "-------------------------------------------------------------------------\n"
- exit 0
- }
- if { $::argc > 0 } {
- for {set i 0} {$i < $::argc} {incr i} {
- set option [string trim [lindex $::argv $i]]
- switch
regexp -$option { - "--origin_dir" { incr i; set origin_dir [lindex $::argv $i] }
- "--project_name" { incr i; set xil_proj_name [lindex $::argv $i] }
- "--help" { print_help }
- default {
- if { [regexp {^-} $option] } {
- puts "ERROR: Unknown option '$option' specified, please type '$script_file -tclargs --help' for usage info.\n"
- return 1
- }
- }
- }
- }
- }
- set orig_proj_dir "[file normalize "$origin_dir/adc_demo"]"
- set validate_required 0
- if { $validate_required } {
- if { [checkRequiredFiles $origin_dir] } {
- puts "Tcl file $script_file is valid. All files required for project creation is accesable. "
- } else {
- puts "Tcl file $script_file is not valid. Not all files required for project creation is accesable. "
- return
- }
- }
- create_project ${_xil_proj_name_} ./${_xil_proj_name_} -part xc7z020clg400-1
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2020.2/data/ip'. - set proj_dir [get_property directory [current_project]]
- set obj [current_project]
- set_property -name "board_part" -value "digilentinc.com:zybo-z7-20:part0:1.0" -objects $obj
- set_property -name "default_lib" -value "xil_defaultlib" -objects $obj
- set_property -name "enable_vhdl_2008" -value "1" -objects $obj
- set_property -name "ip_cache_permissions" -value "read write" -objects $obj
- set_property -name "ip_output_repo" -value "$proj_dir/${_xil_proj_name_}.cache/ip" -objects $obj
- set_property -name "mem.enable_memory_map_generation" -value "1" -objects $obj
- set_property -name "platform.board_id" -value "zybo-z7-20" -objects $obj
- set_property -name "sim.central_dir" -value "$proj_dir/${_xil_proj_name_}.ip_user_files" -objects $obj
- set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj
- set_property -name "simulator_language" -value "Mixed" -objects $obj
- set_property -name "xpm_libraries" -value "XPM_CDC XPM_MEMORY" -objects $obj
- if {[string equal [get_filesets -quiet sources_1] ""]} {
- create_fileset -srcset sources_1
- }
- set obj [get_filesets sources_1]
- set obj [get_filesets sources_1]
- set_property -name "top" -value "design_1_wrapper" -objects $obj
- if {[string equal [get_filesets -quiet constrs_1] ""]} {
- create_fileset -constrset constrs_1
- }
- set obj [get_filesets constrs_1]
- set file "[file normalize "xdc/Zybo-Z7-Master.xdc"]"
- set file_imported [import_files -fileset constrs_1 [list $file]]
- set file "xdc/Zybo-Z7-Master.xdc"
- set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]]
- set_property -name "file_type" -value "XDC" -objects $file_obj
- set obj [get_filesets constrs_1]
WARNING: [Vivado 12-818] No files matched 'xdc/Zybo-Z7-Master.xdc' - set_property -name "target_constrs_file" -value "[get_files xdc/Zybo-Z7-Master.xdc]" -objects $obj
WARNING: [Vivado 12-818] No files matched 'xdc/Zybo-Z7-Master.xdc' - set_property -name "target_ucf" -value "[get_files xdc/Zybo-Z7-Master.xdc]" -objects $obj
- if {[string equal [get_filesets -quiet sim_1] ""]} {
- create_fileset -simset sim_1
- }
- set obj [get_filesets sim_1]
- set obj [get_filesets sim_1]
- set_property -name "hbs.configure_design_for_hier_access" -value "1" -objects $obj
- set_property -name "top" -value "design_1_wrapper" -objects $obj
- set_property -name "top_lib" -value "xil_defaultlib" -objects $obj
- set obj [get_filesets utils_1]
- set obj [get_filesets utils_1]
- proc cr_bd_design_1 { parentCell } {
- # CHANGE DESIGN NAME HERE
- set design_name design_1
- common::send_gid_msg -ssname BD::TCL -id 2010 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..."
- create_bd_design $design_name
- set bCheckIPsPassed 1
- ##################################################################
- # CHECK IPs
- ##################################################################
- set bCheckIPs 1
- if { $bCheckIPs == 1 } {
- set list_check_ips "\
- xilinx.com:ip:processing_system7:5.5\
- xilinx.com:ip:proc_sys_reset:5.0\
- xilinx.com:ip:xadc_wiz:3.3\
- "
- set list_ips_missing ""
- common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
- foreach ip_vlnv $list_check_ips {
- set ip_obj [get_ipdefs -all $ip_vlnv]
- if { $ip_obj eq "" } {
- lappend list_ips_missing $ip_vlnv
- }
- }
- if { $list_ips_missing ne "" } {
- catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP to the project." }
- set bCheckIPsPassed 0
- }
- }
- if { $bCheckIPsPassed != 1 } {
- common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above."
- return 3
- }
- variable script_folder
- if { $parentCell eq "" } {
- set parentCell [get_bd_cells /]
- }
- # Get object for parentCell
- set parentObj [get_bd_cells $parentCell]
- if { $parentObj == "" } {
- catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
- return
- }
- # Make sure parentObj is hier blk
- set parentType [get_property TYPE $parentObj]
- if { $parentType ne "hier" } {
- catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
- return
- }
- # Save current instance; Restore later
- set oldCurInst [current_bd_instance .]
- # Set parent object as current
- current_bd_instance $parentObj
- # Create interface ports
- set DDR [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR ]
- set FIXED_IO [ create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 FIXED_IO ]
- set Vaux6 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vaux6 ]
- set Vaux7 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vaux7 ]
- set Vaux14 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vaux14 ]
- set Vaux15 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vaux15 ]
- # Create ports
- # Create instance: processing_system7_0, and set properties
- set processing_system7_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0 ]
- set_property -dict [ list \
- CONFIG.PCW_ACT_APU_PERIPHERAL_FREQMHZ {666.666687} \
- CONFIG.PCW_ACT_CAN_PERIPHERAL_FREQMHZ {10.000000} \
- CONFIG.PCW_ACT_DCI_PERIPHERAL_FREQMHZ {10.158730} \
- CONFIG.PCW_ACT_ENET0_PERIPHERAL_FREQMHZ {125.000000} \
- CONFIG.PCW_ACT_ENET1_PERIPHERAL_FREQMHZ {10.000000} \
- CONFIG.PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ {50.000000} \
- CONFIG.PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ {10.000000} \
- CONFIG.PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ {10.000000} \
- CONFIG.PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ {10.000000} \
- CONFIG.PCW_ACT_PCAP_PERIPHERAL_FREQMHZ {200.000000} \
- CONFIG.PCW_ACT_QSPI_PERIPHERAL_FREQMHZ {200.000000} \
- CONFIG.PCW_ACT_SDIO_PERIPHERAL_FREQMHZ {50.000000} \
- CONFIG.PCW_ACT_SMC_PERIPHERAL_FREQMHZ {10.000000} \
- CONFIG.PCW_ACT_SPI_PERIPHERAL_FREQMHZ {10.000000} \
- CONFIG.PCW_ACT_TPIU_PERIPHERAL_FREQMHZ {200.000000} \
- CONFIG.PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ {111.111115} \
- CONFIG.PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ {111.111115} \
- CONFIG.PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ {111.111115} \
- CONFIG.PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ {111.111115} \
- CONFIG.PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ {111.111115} \
- CONFIG.PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ {111.111115} \
- CONFIG.PCW_ACT_UART_PERIPHERAL_FREQMHZ {100.000000} \
- CONFIG.PCW_ACT_WDT_PERIPHERAL_FREQMHZ {111.111115} \
- CONFIG.PCW_APU_CLK_RATIO_ENABLE {6:2:1} \
- CONFIG.PCW_APU_PERIPHERAL_FREQMHZ {667} \
- CONFIG.PCW_ARMPLL_CTRL_FBDIV {40} \
- CONFIG.PCW_CAN_PERIPHERAL_DIVISOR0 {1} \
- CONFIG.PCW_CAN_PERIPHERAL_DIVISOR1 {1} \
- CONFIG.PCW_CLK0_FREQ {50000000} \
- CONFIG.PCW_CLK1_FREQ {10000000} \
- CONFIG.PCW_CLK2_FREQ {10000000} \
- CONFIG.PCW_CLK3_FREQ {10000000} \
- CONFIG.PCW_CPU_CPU_6X4X_MAX_RANGE {667} \
- CONFIG.PCW_CPU_CPU_PLL_FREQMHZ {1333.333} \
- CONFIG.PCW_CPU_PERIPHERAL_CLKSRC {ARM PLL} \
- CONFIG.PCW_CPU_PERIPHERAL_DIVISOR0 {2} \
- CONFIG.PCW_CRYSTAL_PERIPHERAL_FREQMHZ {33.333333} \
- CONFIG.PCW_DCI_PERIPHERAL_CLKSRC {DDR PLL} \
- CONFIG.PCW_DCI_PERIPHERAL_DIVISOR0 {15} \
- CONFIG.PCW_DCI_PERIPHERAL_DIVISOR1 {7} \
- CONFIG.PCW_DCI_PERIPHERAL_FREQMHZ {10.159} \
- CONFIG.PCW_DDRPLL_CTRL_FBDIV {32} \
- CONFIG.PCW_DDR_DDR_PLL_FREQMHZ {1066.667} \
- CONFIG.PCW_DDR_HPRLPR_QUEUE_PARTITION {HPR/LPR} \
- CONFIG.PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL {15} \
- CONFIG.PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL {2} \
- CONFIG.PCW_DDR_PERIPHERAL_CLKSRC {DDR PLL} \
- CONFIG.PCW_DDR_PERIPHERAL_DIVISOR0 {2} \
- CONFIG.PCW_DDR_PORT0_HPR_ENABLE {0} \
- CONFIG.PCW_DDR_PORT1_HPR_ENABLE {0} \
- CONFIG.PCW_DDR_PORT2_HPR_ENABLE {0} \
- CONFIG.PCW_DDR_PORT3_HPR_ENABLE {0} \
- CONFIG.PCW_DDR_RAM_HIGHADDR {0x3FFFFFFF} \
- CONFIG.PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL {2} \
- CONFIG.PCW_ENET0_ENET0_IO {MIO 16 .. 27} \
- CONFIG.PCW_ENET0_GRP_MDIO_ENABLE {1} \
- CONFIG.PCW_ENET0_GRP_MDIO_IO {MIO 52 .. 53} \
- CONFIG.PCW_ENET0_PERIPHERAL_CLKSRC {IO PLL} \
- CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR0 {8} \
- CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR1 {1} \
- CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {1} \
- CONFIG.PCW_ENET0_PERIPHERAL_FREQMHZ {1000 Mbps} \
- CONFIG.PCW_ENET0_RESET_ENABLE {0} \
- CONFIG.PCW_ENET1_GRP_MDIO_ENABLE {0} \
- CONFIG.PCW_ENET1_PERIPHERAL_CLKSRC {IO PLL} \
- CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR0 {1} \
- CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR1 {1} \
- CONFIG.PCW_ENET1_PERIPHERAL_ENABLE {0} \
- CONFIG.PCW_ENET1_PERIPHERAL_FREQMHZ {1000 Mbps} \
- CONFIG.PCW_ENET1_RESET_ENABLE {0} \
- CONFIG.PCW_ENET_RESET_ENABLE {1} \
- CONFIG.PCW_ENET_RESET_POLARITY {Active Low} \
- CONFIG.PCW_ENET_RESET_SELECT {Share reset pin} \
- CONFIG.PCW_EN_4K_TIMER {0} \
- CONFIG.PCW_EN_ENET0 {1} \
- CONFIG.PCW_EN_GPIO {1} \
- CONFIG.PCW_EN_QSPI {1} \
- CONFIG.PCW_EN_SDIO0 {1} \
- CONFIG.PCW_EN_UART1 {1} \
- CONFIG.PCW_EN_USB0 {0} \
- CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR0 {5} \
- CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR1 {4} \
- CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR0 {1} \
- CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR1 {1} \
- CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR0 {1} \
- CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR1 {1} \
- CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR0 {1} \
- CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR1 {1} \
- CONFIG.PCW_FPGA_FCLK0_ENABLE {1} \
- CONFIG.PCW_FPGA_FCLK1_ENABLE {0} \
- CONFIG.PCW_FPGA_FCLK2_ENABLE {0} \
- CONFIG.PCW_FPGA_FCLK3_ENABLE {0} \
- CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1} \
- CONFIG.PCW_GPIO_MIO_GPIO_IO {MIO} \
- CONFIG.PCW_GPIO_PERIPHERAL_ENABLE {0} \
- CONFIG.PCW_I2C0_RESET_ENABLE {0} \
- CONFIG.PCW_I2C1_RESET_ENABLE {0} \
- CONFIG.PCW_I2C_PERIPHERAL_FREQMHZ {25} \
- CONFIG.PCW_I2C_RESET_ENABLE {1} \
- CONFIG.PCW_IOPLL_CTRL_FBDIV {30} \
- CONFIG.PCW_IO_IO_PLL_FREQMHZ {1000.000} \
- CONFIG.PCW_IRQ_F2P_MODE {DIRECT} \
- CONFIG.PCW_MIO_0_DIRECTION {inout} \
- CONFIG.PCW_MIO_0_IOTYPE {LVCMOS 3.3V} \
- CONFIG.PCW_MIO_0_PULLUP {enabled} \
- CONFIG.PCW_MIO_0_SLEW {slow} \
- CONFIG.PCW_MIO_10_DIRECTION {inout} \
- CONFIG.PCW_MIO_10_IOTYPE {LVCMOS 3.3V} \
- CONFIG.PCW_MIO_10_PULLUP {enabled} \
- CONFIG.PCW_MIO_10_SLEW {slow} \
- CONFIG.PCW_MIO_11_DIRECTION {inout} \
- CONFIG.PCW_MIO_11_IOTYPE {LVCMOS 3.3V} \
- CONFIG.PCW_MIO_11_PULLUP {enabled} \
- CONFIG.PCW_MIO_11_SLEW {slow} \
- CONFIG.PCW_MIO_12_DIRECTION {inout} \
- CONFIG.PCW_MIO_12_IOTYPE {LVCMOS 3.3V} \
- CONFIG.PCW_MIO_12_PULLUP {enabled} \
- CONFIG.PCW_MIO_12_SLEW {slow} \
- CONFIG.PCW_MIO_13_DIRECTION {inout} \
- CONFIG.PCW_MIO_13_IOTYPE {LVCMOS 3.3V} \
- CONFIG.PCW_MIO_13_PULLUP {enabled} \
- CONFIG.PCW_MIO_13_SLEW {slow} \
- CONFIG.PCW_MIO_14_DIRECTION {inout} \
- CONFIG.PCW_MIO_14_IOTYPE {LVCMOS 3.3V} \
- CONFIG.PCW_MIO_14_PULLUP {enabled} \
- CONFIG.PCW_MIO_14_SLEW {slow} \
- CONFIG.PCW_MIO_15_DIRECTION {inout} \
- CONFIG.PCW_MIO_15_IOTYPE {LVCMOS 3.3V} \
- CONFIG.PCW_MIO_15_PULLUP {enabled} \
- CONFIG.PCW_MIO_15_SLEW {slow} \
- CONFIG.PCW_MIO_16_DIRECTION {out} \
- CONFIG.PCW_MIO_16_IOTYPE {LVCMOS 1.8V} \
- CONFIG.PCW_MIO_16_PULLUP {enabled} \
- CONFIG.PCW_MIO_16_SLEW {fast} \
- CONFIG.PCW_MIO_17_DIRECTION {out} \
- CONFIG.PCW_MIO_17_IOTYPE {LVCMOS 1.8V} \
- CONFIG.PCW_MIO_17_PULLUP {enabled} \
- CONFIG.PCW_MIO_17_SLEW {fast} \
- CONFIG.PCW_MIO_18_DIRECTION {out} \
- CONFIG.PCW_MIO_18_IOTYPE {LVCMOS 1.8V} \
- CONFIG.PCW_MIO_18_PULLUP {enabled} \
- CONFIG.PCW_MIO_18_SLEW {fast} \
- CONFIG.PCW_MIO_19_DIRECTION {out} \
- CONFIG.PCW_MIO_19_IOTYPE {LVCMOS 1.8V} \
- CONFIG.PCW_MIO_19_PULLUP {enabled} \
- CONFIG.PCW_MIO_19_SLEW {fast} \
- CONFIG.PCW_MIO_1_DIRECTION {out} \
- CONFIG.PCW_MIO_1_IOTYPE {LVCMOS 3.3V} \
- CONFIG.PCW_MIO_1_PULLUP {enabled} \
- CONFIG.PCW_MIO_1_SLEW {slow} \
- CONFIG.PCW_MIO_20_DIRECTION {out} \
- CONFIG.PCW_MIO_20_IOTYPE {LVCMOS 1.8V} \
- CONFIG.PCW_MIO_20_PULLUP {enabled} \
- CONFIG.PCW_MIO_20_SLEW {fast} \
- CONFIG.PCW_MIO_21_DIRECTION {out} \
- CONFIG.PCW_MIO_21_IOTYPE {LVCMOS 1.8V} \
- CONFIG.PCW_MIO_21_PULLUP {enabled} \
- CONFIG.PCW_MIO_21_SLEW {fast} \
- CONFIG.PCW_MIO_22_DIRECTION {in} \
- CONFIG.PCW_MIO_22_IOTYPE {LVCMOS 1.8V} \
- CONFIG.PCW_MIO_22_PULLUP {enabled} \
- CONFIG.PCW_MIO_22_SLEW {fast} \
- CONFIG.PCW_MIO_23_DIRECTION {in} \
- CONFIG.PCW_MIO_23_IOTYPE {LVCMOS 1.8V} \
- CONFIG.PCW_MIO_23_PULLUP {enabled} \
- CONFIG.PCW_MIO_23_SLEW {fast} \
- CONFIG.PCW_MIO_24_DIRECTION {in} \
- CONFIG.PCW_MIO_24_IOTYPE {LVCMOS 1.8V} \
- CONFIG.PCW_MIO_24_PULLUP {enabled} \
- CONFIG.PCW_MIO_24_SLEW {fast} \
- CONFIG.PCW_MIO_25_DIRECTION {in} \
- CONFIG.PCW_MIO_25_IOTYPE {LVCMOS 1.8V} \
- CONFIG.PCW_MIO_25_PULLUP {enabled} \
- CONFIG.PCW_MIO_25_SLEW {fast} \
- CONFIG.PCW_MIO_26_DIRECTION {in} \
- CONFIG.PCW_MIO_26_IOTYPE {LVCMOS 1.8V} \
- CONFIG.PCW_MIO_26_PULLUP {enabled} \
- CONFIG.PCW_MIO_26_SLEW {fast} \
- CONFIG.PCW_MIO_27_DIRECTION {in} \
- CONFIG.PCW_MIO_27_IOTYPE {LVCMOS 1.8V} \
- CONFIG.PCW_MIO_27_PULLUP {enabled} \
- CONFIG.PCW_MIO_27_SLEW {fast} \
- CONFIG.PCW_MIO_28_DIRECTION {inout} \
- CONFIG.PCW_MIO_28_IOTYPE {LVCMOS 1.8V} \
- CONFIG.PCW_MIO_28_PULLUP {enabled} \
- CONFIG.PCW_MIO_28_SLEW {fast} \
- CONFIG.PCW_MIO_29_DIRECTION {in} \
- CONFIG.PCW_MIO_29_IOTYPE {LVCMOS 1.8V} \
- CONFIG.PCW_MIO_29_PULLUP {enabled} \
- CONFIG.PCW_MIO_29_SLEW {fast} \
- CONFIG.PCW_MIO_2_DIRECTION {inout} \
- CONFIG.PCW_MIO_2_IOTYPE {LVCMOS 3.3V} \
- CONFIG.PCW_MIO_2_PULLUP {disabled} \
- CONFIG.PCW_MIO_2_SLEW {slow} \
- CONFIG.PCW_MIO_30_DIRECTION {out} \
- CONFIG.PCW_MIO_30_IOTYPE {LVCMOS 1.8V} \
- CONFIG.PCW_MIO_30_PULLUP {enabled} \
- CONFIG.PCW_MIO_30_SLEW {fast} \
- CONFIG.PCW_MIO_31_DIRECTION {in} \
- CONFIG.PCW_MIO_31_IOTYPE {LVCMOS 1.8V} \
- CONFIG.PCW_MIO_31_PULLUP {enabled} \
- CONFIG.PCW_MIO_31_SLEW {fast} \
- CONFIG.PCW_MIO_32_DIRECTION {inout} \
- CONFIG.PCW_MIO_32_IOTYPE {LVCMOS 1.8V} \
- CONFIG.PCW_MIO_32_PULLUP {enabled} \
- CONFIG.PCW_MIO_32_SLEW {fast} \
- CONFIG.PCW_MIO_33_DIRECTION {inout} \
- CONFIG.PCW_MIO_33_IOTYPE {LVCMOS 1.8V} \
- CONFIG.PCW_MIO_33_PULLUP {enabled} \
- CONFIG.PCW_MIO_33_SLEW {fast} \
- CONFIG.PCW_MIO_34_DIRECTION {inout} \
- CONFIG.PCW_MIO_34_IOTYPE {LVCMOS 1.8V} \
- CONFIG.PCW_MIO_34_PULLUP {enabled} \
- CONFIG.PCW_MIO_34_SLEW {fast} \
- CONFIG.PCW_MIO_35_DIRECTION {inout} \
- CONFIG.PCW_MIO_35_IOTYPE {LVCMOS 1.8V} \
- CONFIG.PCW_MIO_35_PULLUP {enabled} \
- CONFIG.PCW_MIO_35_SLEW {fast} \
- CONFIG.PCW_MIO_36_DIRECTION {in} \
- CONFIG.PCW_MIO_36_IOTYPE {LVCMOS 1.8V} \
- CONFIG.PCW_MIO_36_PULLUP {enabled} \
- CONFIG.PCW_MIO_36_SLEW {fast} \
- CONFIG.PCW_MIO_37_DIRECTION {inout} \
- CONFIG.PCW_MIO_37_IOTYPE {LVCMOS 1.8V} \
- CONFIG.PCW_MIO_37_PULLUP {enabled} \
- CONFIG.PCW_MIO_37_SLEW {fast} \
- CONFIG.PCW_MIO_38_DIRECTION {inout} \
- CONFIG.PCW_MIO_38_IOTYPE {LVCMOS 1.8V} \
- CONFIG.PCW_MIO_38_PULLUP {enabled} \
- CONFIG.PCW_MIO_38_SLEW {fast} \
- CONFIG.PCW_MIO_39_DIRECTION {inout} \
- CONFIG.PCW_MIO_39_IOTYPE {LVCMOS 1.8V} \
- CONFIG.PCW_MIO_39_PULLUP {enabled} \
- CONFIG.PCW_MIO_39_SLEW {fast} \
- CONFIG.PCW_MIO_3_DIRECTION {inout} \
- CONFIG.PCW_MIO_3_IOTYPE {LVCMOS 3.3V} \
- CONFIG.PCW_MIO_3_PULLUP {disabled} \
- CONFIG.PCW_MIO_3_SLEW {slow} \
- CONFIG.PCW_MIO_40_DIRECTION {inout} \
- CONFIG.PCW_MIO_40_IOTYPE {LVCMOS 1.8V} \
- CONFIG.PCW_MIO_40_PULLUP {enabled} \
- CONFIG.PCW_MIO_40_SLEW {slow} \
- CONFIG.PCW_MIO_41_DIRECTION {inout} \
- CONFIG.PCW_MIO_41_IOTYPE {LVCMOS 1.8V} \
- CONFIG.PCW_MIO_41_PULLUP {enabled} \
- CONFIG.PCW_MIO_41_SLEW {slow} \
- CONFIG.PCW_MIO_42_DIRECTION {inout} \
- CONFIG.PCW_MIO_42_IOTYPE {LVCMOS 1.8V} \
- CONFIG.PCW_MIO_42_PULLUP {enabled} \
- CONFIG.PCW_MIO_42_SLEW {slow} \
- CONFIG.PCW_MIO_43_DIRECTION {inout} \
- CONFIG.PCW_MIO_43_IOTYPE {LVCMOS 1.8V} \
- CONFIG.PCW_MIO_43_PULLUP {enabled} \
- CONFIG.PCW_MIO_43_SLEW {slow} \
- CONFIG.PCW_MIO_44_DIRECTION {inout} \
- CONFIG.PCW_MIO_44_IOTYPE {LVCMOS 1.8V} \
- CONFIG.PCW_MIO_44_PULLUP {enabled} \
- CONFIG.PCW_MIO_44_SLEW {slow} \
- CONFIG.PCW_MIO_45_DIRECTION {inout} \
- CONFIG.PCW_MIO_45_IOTYPE {LVCMOS 1.8V} \
- CONFIG.PCW_MIO_45_PULLUP {enabled} \
- CONFIG.PCW_MIO_45_SLEW {slow} \
- CONFIG.PCW_MIO_46_DIRECTION {out} \
- CONFIG.PCW_MIO_46_IOTYPE {LVCMOS 1.8V} \
- CONFIG.PCW_MIO_46_PULLUP {enabled} \
- CONFIG.PCW_MIO_46_SLEW {slow} \
- CONFIG.PCW_MIO_47_DIRECTION {in} \
- CONFIG.PCW_MIO_47_IOTYPE {LVCMOS 1.8V} \
- CONFIG.PCW_MIO_47_PULLUP {enabled} \
- CONFIG.PCW_MIO_47_SLEW {slow} \
- CONFIG.PCW_MIO_48_DIRECTION {out} \
- CONFIG.PCW_MIO_48_IOTYPE {LVCMOS 1.8V} \
- CONFIG.PCW_MIO_48_PULLUP {enabled} \
- CONFIG.PCW_MIO_48_SLEW {slow} \
- CONFIG.PCW_MIO_49_DIRECTION {in} \
- CONFIG.PCW_MIO_49_IOTYPE {LVCMOS 1.8V} \
- CONFIG.PCW_MIO_49_PULLUP {enabled} \
- CONFIG.PCW_MIO_49_SLEW {slow} \
- CONFIG.PCW_MIO_4_DIRECTION {inout} \
- CONFIG.PCW_MIO_4_IOTYPE {LVCMOS 3.3V} \
- CONFIG.PCW_MIO_4_PULLUP {disabled} \
- CONFIG.PCW_MIO_4_SLEW {slow} \
- CONFIG.PCW_MIO_50_DIRECTION {inout} \
- CONFIG.PCW_MIO_50_IOTYPE {LVCMOS 1.8V} \
- CONFIG.PCW_MIO_50_PULLUP {enabled} \
- CONFIG.PCW_MIO_50_SLEW {slow} \
- CONFIG.PCW_MIO_51_DIRECTION {inout} \
- CONFIG.PCW_MIO_51_IOTYPE {LVCMOS 1.8V} \
- CONFIG.PCW_MIO_51_PULLUP {enabled} \
- CONFIG.PCW_MIO_51_SLEW {slow} \
- CONFIG.PCW_MIO_52_DIRECTION {out} \
- CONFIG.PCW_MIO_52_IOTYPE {LVCMOS 1.8V} \
- CONFIG.PCW_MIO_52_PULLUP {enabled} \
- CONFIG.PCW_MIO_52_SLEW {slow} \
- CONFIG.PCW_MIO_53_DIRECTION {inout} \
- CONFIG.PCW_MIO_53_IOTYPE {LVCMOS 1.8V} \
- CONFIG.PCW_MIO_53_PULLUP {enabled} \
- CONFIG.PCW_MIO_53_SLEW {slow} \
- CONFIG.PCW_MIO_5_DIRECTION {inout} \
- CONFIG.PCW_MIO_5_IOTYPE {LVCMOS 3.3V} \
- CONFIG.PCW_MIO_5_PULLUP {disabled} \
- CONFIG.PCW_MIO_5_SLEW {slow} \
- CONFIG.PCW_MIO_6_DIRECTION {out} \
- CONFIG.PCW_MIO_6_IOTYPE {LVCMOS 3.3V} \
- CONFIG.PCW_MIO_6_PULLUP {disabled} \
- CONFIG.PCW_MIO_6_SLEW {slow} \
- CONFIG.PCW_MIO_7_DIRECTION {out} \
- CONFIG.PCW_MIO_7_IOTYPE {LVCMOS 3.3V} \
- CONFIG.PCW_MIO_7_PULLUP {disabled} \
- CONFIG.PCW_MIO_7_SLEW {slow} \
- CONFIG.PCW_MIO_8_DIRECTION {out} \
- CONFIG.PCW_MIO_8_IOTYPE {LVCMOS 3.3V} \
- CONFIG.PCW_MIO_8_PULLUP {disabled} \
- CONFIG.PCW_MIO_8_SLEW {slow} \
- CONFIG.PCW_MIO_9_DIRECTION {inout} \
- CONFIG.PCW_MIO_9_IOTYPE {LVCMOS 3.3V} \
- CONFIG.PCW_MIO_9_PULLUP {enabled} \
- CONFIG.PCW_MIO_9_SLEW {slow} \
- CONFIG.PCW_MIO_TREE_PERIPHERALS { \
- 0#Enet 0 \
- 0#Enet 0 \
- 0#Enet 0 \
- 0#Enet 0 \
- 0#Enet 0 \
- 0#Enet 0 \
- 0#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#SD 0#SD \
- 0#GPIO#SD 0#UART \
- 0#SD 0#SD \
- 0#SD 0#SD \
- 1#UART 1#GPIO#GPIO#Enet \
- Flash#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#Enet 0#Enet \
- Flash#GPIO#Quad SPI \
- Flash#Quad SPI \
- Flash#Quad SPI \
- Flash#Quad SPI \
- Flash#Quad SPI \
- Flash#Quad SPI \
- GPIO#Quad SPI \
- } \
- CONFIG.PCW_MIO_TREE_SIGNALS {gpio0#qspi0_ss_b#qspi0_io0#qspi0_io1#qspi0_io2#qspi0_io3/HOLD_B#qspi0_sclk#gpio7#qspi_fbclk#gpio9#gpio10#gpio11#gpio12#gpio13#gpio14#gpio15#tx_clk#txd0#txd1#txd2#txd3#tx_ctl#rx_clk#rxd0#rxd1#rxd2#rxd3#rx_ctl#gpio28#gpio29#gpio30#gpio31#gpio32#gpio33#gpio34#gpio35#gpio36#gpio37#gpio38#gpio39#clk#cmd#data0#data1#data2#data3#gpio46#cd#tx#rx#gpio50#gpio51#mdc#mdio} \
- CONFIG.PCW_NAND_GRP_D8_ENABLE {0} \
- CONFIG.PCW_NAND_PERIPHERAL_ENABLE {0} \
- CONFIG.PCW_NOR_GRP_A25_ENABLE {0} \
- CONFIG.PCW_NOR_GRP_CS0_ENABLE {0} \
- CONFIG.PCW_NOR_GRP_CS1_ENABLE {0} \
- CONFIG.PCW_NOR_GRP_SRAM_CS0_ENABLE {0} \
- CONFIG.PCW_NOR_GRP_SRAM_CS1_ENABLE {0} \
- CONFIG.PCW_NOR_GRP_SRAM_INT_ENABLE {0} \
- CONFIG.PCW_NOR_PERIPHERAL_ENABLE {0} \
- CONFIG.PCW_OVERRIDE_BASIC_CLOCK {0} \
- CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY0 {0.221} \
- CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY1 {0.222} \
- CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY2 {0.217} \
- CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY3 {0.244} \
- CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_0 {-0.050} \
- CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_1 {-0.044} \
- CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_2 {-0.035} \
- CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_3 {-0.100} \
- CONFIG.PCW_PCAP_PERIPHERAL_CLKSRC {IO PLL} \
- CONFIG.PCW_PCAP_PERIPHERAL_DIVISOR0 {5} \
- CONFIG.PCW_PCAP_PERIPHERAL_FREQMHZ {200} \
- CONFIG.PCW_PJTAG_PERIPHERAL_ENABLE {0} \
- CONFIG.PCW_PLL_BYPASSMODE_ENABLE {0} \
- CONFIG.PCW_PRESET_BANK0_VOLTAGE {LVCMOS 3.3V} \
- CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 1.8V} \
- CONFIG.PCW_QSPI_GRP_FBCLK_ENABLE {1} \
- CONFIG.PCW_QSPI_GRP_FBCLK_IO {MIO 8} \
- CONFIG.PCW_QSPI_GRP_IO1_ENABLE {0} \
- CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE {1} \
- CONFIG.PCW_QSPI_GRP_SINGLE_SS_IO {MIO 1 .. 6} \
- CONFIG.PCW_QSPI_GRP_SS1_ENABLE {0} \
- CONFIG.PCW_QSPI_INTERNAL_HIGHADDRESS {0xFCFFFFFF} \
- CONFIG.PCW_QSPI_PERIPHERAL_CLKSRC {IO PLL} \
- CONFIG.PCW_QSPI_PERIPHERAL_DIVISOR0 {5} \
- CONFIG.PCW_QSPI_PERIPHERAL_ENABLE {1} \
- CONFIG.PCW_QSPI_PERIPHERAL_FREQMHZ {200} \
- CONFIG.PCW_QSPI_QSPI_IO {MIO 1 .. 6} \
- CONFIG.PCW_SD0_GRP_CD_ENABLE {1} \
- CONFIG.PCW_SD0_GRP_CD_IO {MIO 47} \
- CONFIG.PCW_SD0_GRP_POW_ENABLE {0} \
- CONFIG.PCW_SD0_GRP_WP_ENABLE {0} \
- CONFIG.PCW_SD0_PERIPHERAL_ENABLE {1} \
- CONFIG.PCW_SD0_SD0_IO {MIO 40 .. 45} \
- CONFIG.PCW_SDIO_PERIPHERAL_CLKSRC {IO PLL} \
- CONFIG.PCW_SDIO_PERIPHERAL_DIVISOR0 {20} \
- CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ {50} \
- CONFIG.PCW_SDIO_PERIPHERAL_VALID {1} \
- CONFIG.PCW_SINGLE_QSPI_DATA_MODE {x4} \
- CONFIG.PCW_SMC_PERIPHERAL_CLKSRC {IO PLL} \
- CONFIG.PCW_SMC_PERIPHERAL_DIVISOR0 {1} \
- CONFIG.PCW_SMC_PERIPHERAL_FREQMHZ {100} \
- CONFIG.PCW_SPI_PERIPHERAL_DIVISOR0 {1} \
- CONFIG.PCW_TPIU_PERIPHERAL_CLKSRC {External} \
- CONFIG.PCW_TPIU_PERIPHERAL_DIVISOR0 {1} \
- CONFIG.PCW_TPIU_PERIPHERAL_FREQMHZ {200} \
- CONFIG.PCW_UART0_GRP_FULL_ENABLE {0} \
- CONFIG.PCW_UART0_PERIPHERAL_ENABLE {0} \
- CONFIG.PCW_UART1_BAUD_RATE {115200} \
- CONFIG.PCW_UART1_GRP_FULL_ENABLE {0} \
- CONFIG.PCW_UART1_PERIPHERAL_ENABLE {1} \
- CONFIG.PCW_UART1_UART1_IO {MIO 48 .. 49} \
- CONFIG.PCW_UART_PERIPHERAL_CLKSRC {IO PLL} \
- CONFIG.PCW_UART_PERIPHERAL_DIVISOR0 {10} \
- CONFIG.PCW_UART_PERIPHERAL_FREQMHZ {100} \
- CONFIG.PCW_UART_PERIPHERAL_VALID {1} \
- CONFIG.PCW_UIPARAM_ACT_DDR_FREQ_MHZ {533.333374} \
- CONFIG.PCW_UIPARAM_DDR_ADV_ENABLE {0} \
- CONFIG.PCW_UIPARAM_DDR_AL {0} \
- CONFIG.PCW_UIPARAM_DDR_BANK_ADDR_COUNT {3} \
- CONFIG.PCW_UIPARAM_DDR_BL {8} \
- CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0 {0.221} \
- CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1 {0.222} \
- CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2 {0.217} \
- CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3 {0.244} \
- CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH {32 Bit} \
- CONFIG.PCW_UIPARAM_DDR_CL {7} \
- CONFIG.PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM {18.8} \
- CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH {80.4535} \
- CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY {160} \
- CONFIG.PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM {18.8} \
- CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH {80.4535} \
- CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY {160} \
- CONFIG.PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM {18.8} \
- CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH {80.4535} \
- CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY {160} \
- CONFIG.PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM {18.8} \
- CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH {80.4535} \
- CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY {160} \
- CONFIG.PCW_UIPARAM_DDR_CLOCK_STOP_EN {0} \
- CONFIG.PCW_UIPARAM_DDR_COL_ADDR_COUNT {10} \
- CONFIG.PCW_UIPARAM_DDR_CWL {6} \
- CONFIG.PCW_UIPARAM_DDR_DEVICE_CAPACITY {4096 MBits} \
- CONFIG.PCW_UIPARAM_DDR_DQS_0_LENGTH_MM {22.8} \
- CONFIG.PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH {105.056} \
- CONFIG.PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY {160} \
- CONFIG.PCW_UIPARAM_DDR_DQS_1_LENGTH_MM {27.9} \
- CONFIG.PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH {66.904} \
- CONFIG.PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY {160} \
- CONFIG.PCW_UIPARAM_DDR_DQS_2_LENGTH_MM {22.9} \
- CONFIG.PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH {89.1715} \
- CONFIG.PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY {160} \
- CONFIG.PCW_UIPARAM_DDR_DQS_3_LENGTH_MM {29.4} \
- CONFIG.PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH {113.63} \
- CONFIG.PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY {160} \
- CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 {-0.050} \
- CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 {-0.044} \
- CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 {-0.035} \
- CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 {-0.100} \
- CONFIG.PCW_UIPARAM_DDR_DQ_0_LENGTH_MM {22.8} \
- CONFIG.PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH {98.503} \
- CONFIG.PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY {160} \
- CONFIG.PCW_UIPARAM_DDR_DQ_1_LENGTH_MM {27.9} \
- CONFIG.PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH {68.5855} \
- CONFIG.PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY {160} \
- CONFIG.PCW_UIPARAM_DDR_DQ_2_LENGTH_MM {22.9} \
- CONFIG.PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH {90.295} \
- CONFIG.PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY {160} \
- CONFIG.PCW_UIPARAM_DDR_DQ_3_LENGTH_MM {29.4} \
- CONFIG.PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH {103.977} \
- CONFIG.PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY {160} \
- CONFIG.PCW_UIPARAM_DDR_DRAM_WIDTH {16 Bits} \
- CONFIG.PCW_UIPARAM_DDR_ECC {Disabled} \
- CONFIG.PCW_UIPARAM_DDR_ENABLE {1} \
- CONFIG.PCW_UIPARAM_DDR_FREQ_MHZ {533.333333} \
- CONFIG.PCW_UIPARAM_DDR_HIGH_TEMP {Normal (0-85)} \
- CONFIG.PCW_UIPARAM_DDR_MEMORY_TYPE {DDR 3 (Low Voltage)} \
- CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41K256M16 RE-125} \
- CONFIG.PCW_UIPARAM_DDR_ROW_ADDR_COUNT {15} \
- CONFIG.PCW_UIPARAM_DDR_SPEED_BIN {DDR3_1066F} \
- CONFIG.PCW_UIPARAM_DDR_TRAIN_DATA_EYE {1} \
- CONFIG.PCW_UIPARAM_DDR_TRAIN_READ_GATE {1} \
- CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL {1} \
- CONFIG.PCW_UIPARAM_DDR_T_FAW {40.0} \
- CONFIG.PCW_UIPARAM_DDR_T_RAS_MIN {35.0} \
- CONFIG.PCW_UIPARAM_DDR_T_RC {48.75} \
- CONFIG.PCW_UIPARAM_DDR_T_RCD {7} \
- CONFIG.PCW_UIPARAM_DDR_T_RP {7} \
- CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF {0} \
- CONFIG.PCW_USB0_PERIPHERAL_ENABLE {0} \
- CONFIG.PCW_USB0_PERIPHERAL_FREQMHZ {60} \
- CONFIG.PCW_USB0_RESET_ENABLE {1} \
- CONFIG.PCW_USB0_RESET_IO {MIO 46} \
- CONFIG.PCW_USB0_USB0_IO {<Select>} \
- CONFIG.PCW_USB1_RESET_ENABLE {0} \
- CONFIG.PCW_USB_RESET_ENABLE {1} \
- CONFIG.PCW_USB_RESET_POLARITY {Active Low} \
- CONFIG.PCW_USB_RESET_SELECT {<Select>} \
- CONFIG.PCW_USE_AXI_NONSECURE {0} \
- CONFIG.PCW_USE_CROSS_TRIGGER {0} \
- CONFIG.PCW_USE_M_AXI_GP0 {1} \
- ] $processing_system7_0
- # Create instance: ps7_0_axi_periph, and set properties
- set ps7_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 ps7_0_axi_periph ]
- set_property -dict [ list \
- CONFIG.NUM_MI {1} \
- ] $ps7_0_axi_periph
- # Create instance: rst_ps7_0_50M, and set properties
- set rst_ps7_0_50M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_ps7_0_50M ]
- # Create instance: xadc_wiz_0, and set properties
- set xadc_wiz_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xadc_wiz:3.3 xadc_wiz_0 ]
- set_property -dict [ list \
- CONFIG.ADC_OFFSET_AND_GAIN_CALIBRATION {false} \
- CONFIG.CHANNEL_ENABLE_VAUXP14_VAUXN14 {true} \
- CONFIG.CHANNEL_ENABLE_VAUXP15_VAUXN15 {true} \
- CONFIG.CHANNEL_ENABLE_VAUXP6_VAUXN6 {true} \
- CONFIG.CHANNEL_ENABLE_VAUXP7_VAUXN7 {true} \
- CONFIG.CHANNEL_ENABLE_VP_VN {false} \
- CONFIG.ENABLE_CALIBRATION_AVERAGING {false} \
- CONFIG.ENABLE_VCCDDRO_ALARM {false} \
- CONFIG.ENABLE_VCCPAUX_ALARM {false} \
- CONFIG.ENABLE_VCCPINT_ALARM {false} \
- CONFIG.EXTERNAL_MUX_CHANNEL {VP_VN} \
- CONFIG.OT_ALARM {false} \
- CONFIG.SENSOR_OFFSET_AND_GAIN_CALIBRATION {false} \
- CONFIG.SEQUENCER_MODE {Continuous} \
- CONFIG.SINGLE_CHANNEL_SELECTION {TEMPERATURE} \
- CONFIG.USER_TEMP_ALARM {false} \
- CONFIG.VCCAUX_ALARM {false} \
- CONFIG.VCCINT_ALARM {false} \
- CONFIG.XADC_STARUP_SELECTION {channel_sequencer} \
- ] $xadc_wiz_0
- # Create interface connections
- connect_bd_intf_net -intf_net Vaux14_1 [get_bd_intf_ports Vaux14] [get_bd_intf_pins xadc_wiz_0/Vaux14]
- connect_bd_intf_net -intf_net Vaux15_1 [get_bd_intf_ports Vaux15] [get_bd_intf_pins xadc_wiz_0/Vaux15]
- connect_bd_intf_net -intf_net Vaux6_1 [get_bd_intf_ports Vaux6] [get_bd_intf_pins xadc_wiz_0/Vaux6]
- connect_bd_intf_net -intf_net Vaux7_1 [get_bd_intf_ports Vaux7] [get_bd_intf_pins xadc_wiz_0/Vaux7]
- connect_bd_intf_net -intf_net processing_system7_0_DDR [get_bd_intf_ports DDR] [get_bd_intf_pins processing_system7_0/DDR]
- connect_bd_intf_net -intf_net processing_system7_0_FIXED_IO [get_bd_intf_ports FIXED_IO] [get_bd_intf_pins processing_system7_0/FIXED_IO]
- connect_bd_intf_net -intf_net processing_system7_0_M_AXI_GP0 [get_bd_intf_pins processing_system7_0/M_AXI_GP0] [get_bd_intf_pins ps7_0_axi_periph/S00_AXI]
- connect_bd_intf_net -intf_net ps7_0_axi_periph_M00_AXI [get_bd_intf_pins ps7_0_axi_periph/M00_AXI] [get_bd_intf_pins xadc_wiz_0/s_axi_lite]
- # Create port connections
- connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins ps7_0_axi_periph/ACLK] [get_bd_pins ps7_0_axi_periph/M00_ACLK] [get_bd_pins ps7_0_axi_periph/S00_ACLK] [get_bd_pins rst_ps7_0_50M/slowest_sync_clk] [get_bd_pins xadc_wiz_0/s_axi_aclk]
- connect_bd_net -net processing_system7_0_FCLK_RESET0_N [get_bd_pins processing_system7_0/FCLK_RESET0_N] [get_bd_pins rst_ps7_0_50M/ext_reset_in]
- connect_bd_net -net rst_ps7_0_50M_peripheral_aresetn [get_bd_pins ps7_0_axi_periph/ARESETN] [get_bd_pins ps7_0_axi_periph/M00_ARESETN] [get_bd_pins ps7_0_axi_periph/S00_ARESETN] [get_bd_pins rst_ps7_0_50M/peripheral_aresetn] [get_bd_pins xadc_wiz_0/s_axi_aresetn]
- # Create address segments
- assign_bd_address -offset 0x43C00000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs xadc_wiz_0/s_axi_lite/Reg] -force
- # Perform GUI Layout
- regenerate_bd_layout -layout_string {
- "ActiveEmotionalView":"Default View",
- "Default View_ScaleFactor":"0.951852",
- "Default View_TopLeft":"-139,30",
- "ExpandedHierarchyInLayout":"",
- "guistr":"# # String gsaved with Nlview 7.0r6 2020-01-29 bk=1.5227 VDI=41 GEI=36 GUI=JA:10.0 non-TLS
- # -string -flagsOSRD
- preplace port DDR -pg 1 -lvl 4 -x 1080 -y 60 -defaultsOSRD
- preplace port FIXED_IO -pg 1 -lvl 4 -x 1080 -y 80 -defaultsOSRD
- preplace port Vaux6 -pg 1 -lvl 0 -x -10 -y 210 -defaultsOSRD
- preplace port Vaux7 -pg 1 -lvl 0 -x -10 -y 420 -defaultsOSRD
- preplace port Vaux14 -pg 1 -lvl 0 -x -10 -y 470 -defaultsOSRD
- preplace port Vaux15 -pg 1 -lvl 0 -x -10 -y 490 -defaultsOSRD
- preplace inst processing_system7_0 -pg 1 -lvl 1 -x 230 -y 100 -defaultsOSRD
- preplace inst xadc_wiz_0 -pg 1 -lvl 3 -x 930 -y 410 -defaultsOSRD
- preplace inst ps7_0_axi_periph -pg 1 -lvl 2 -x 610 -y 340 -defaultsOSRD
- preplace inst rst_ps7_0_50M -pg 1 -lvl 1 -x 230 -y 320 -defaultsOSRD
- preplace netloc processing_system7_0_FCLK_CLK0 1 0 3 20 430 440 480 790
- preplace netloc processing_system7_0_FCLK_RESET0_N 1 0 2 30 420 430
- preplace netloc rst_ps7_0_50M_peripheral_aresetn 1 1 2 450 500 800J
- preplace netloc processing_system7_0_DDR 1 1 3 NJ 60 NJ 60 NJ
- preplace netloc processing_system7_0_FIXED_IO 1 1 3 NJ 80 NJ 80 NJ
- preplace netloc processing_system7_0_M_AXI_GP0 1 1 1 450 100n
- preplace netloc ps7_0_axi_periph_M00_AXI 1 2 1 N 340
- preplace netloc Vaux6_1 1 0 3 NJ 210 NJ 210 760J
- preplace netloc Vaux7_1 1 0 3 10J 460 NJ 460 760J
- preplace netloc Vaux14_1 1 0 3 NJ 470 NJ 470 770J
- preplace netloc Vaux15_1 1 0 3 NJ 490 NJ 490 780J
- levelinfo -pg 1 -10 230 610 930 1080
- pagesize -pg 1 -db -bbox -sgen -110 0 1200 540
- "
- }
- # Restore current instance
- current_bd_instance $oldCurInst
- validate_bd_design
- save_bd_design
- close_bd_design $design_name
- }
- cr_bd_design_1 ""
INFO: [BD::TCL 103-2010] Currently there is no design <design_1> in project, so creating one...
Wrote : <C:\AimaginProjects\Z7000\adc_demo\hardware_design\vivado_tcl\adc_demo\adc_demo.srcs\sources_1\bd\design_1\design_1.bd>
create_bd_design: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 1138.055 ; gain = 0.000
INFO: [BD::TCL 103-2011] Checking if the following IPs exist in the project's IP catalog:
xilinx.com:ip:processing_system7:5.5 xilinx.com:ip:proc_sys_reset:5.0 xilinx.com:ip:xadc_wiz:3.3 .
WARNING: [IP_Flow 19-3331] Invalid parameters found in dependency constraints of 'ADDRBLOCK_RANGE.S_AXI_ACP.ACP_QSPI_LINEAR'
WARNING: [IP_Flow 19-3331] Invalid parameters found in dependency constraints of 'ADDRBLOCK_RANGE.S_AXI_ACP.ACP_QSPI_LINEAR'
WARNING: [IP_Flow 19-3553] Error found in parameter dependencies in XGUI files.
ERROR: [IP_Flow 19-3428] Failed to create Customization object design_1_processing_system7_0_0
CRITICAL WARNING: [IP_Flow 19-5622] Failed to create IP instance 'design_1_processing_system7_0_0'. Failed to customize IP instance 'design_1_processing_system7_0_0'. Failed to load customization data
ERROR: [BD 41-1712] Create IP failed with errors
ERROR: [BD 5-7] Error: running create_bd_cell -vlnv xilinx.com:ip:processing_system7:5.5 -type ip -name processing_system7_0 .
ERROR: [Common 17-39] 'create_bd_cell' failed due to earlier errors.while executing
"create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0 "
(procedure "cr_bd_design_1" line 85)
invoked from within
"cr_bd_design_1 """
(file "zybo7z20_adc_demo.tcl" line 885)
update_compile_order -fileset sources_1
Any suggestions about what went wrong?
Regards,
johan.
RE: Errors when generating .xsa file (adc_demo project) - Added by Shawn Sebastian Pulle (ฌอน) over 1 year ago
Hi Johan,
It looks like the tcl script is failing when it is trying to add an IP core to the design.
Two of the probable causes for this would be,
1) Something is wrong with the installation (files not installed/ not in the expect location etc.)
2) certain settings in the operating system is causing this issue
First, please try to create a design in vivado manually, without using the tcl.
If this produces errors (errors will pop up on the tcl window when adding the ip block etc.), then this confirms above two reasons as the most probable causes.
At this stage it is a problem with vivado itself not the tcl file. Best approach here would be to seek help and information from xilinx support. https://support.xilinx.com/s/?language=en_US
From my brief research on xilinx forums, there are 2 things you can try. Please note these are suggestions that you may try at your own risk. As mentioned before, best step would be to ask xilinx support .
1) open the run window (Ctrl+R) and run "intl.cpl". (This is a solution I found on the xilinx forums. https://support.xilinx.com/s/question/0D52E00006hpkZlSAI/re-fails-to-load-include-zynq7-processing-system-ip-in-block-design?language=en_US)
In the window that pops up select "Change system locale"
Deselect Beta tick box and make sure the system locale is set to English (United States)
This has fixed this issue for some users.
2) Alternatively you can try reinstalling vivado (if you suspect there is a chance some options were not selected during installation and might be causing this issue)
If you are uncomfortable making changes to the operating system or need an explanation as to what exactly is the cause of this issue, it would be best to approach xilinx with this inquiry. If you do decide to do that, please keep us informed of your findings as well.
Best Regards,
Shawn
RE: Errors when generating .xsa file (adc_demo project) - Added by Johan Henning over 1 year ago
Hello Shawn,
I tried generating a project from scratch -> no success
Then I uninstallen and reinstalled Xilinx and added the boards again (version 1.0, not version 1.1)
Same problem occurred
Then I tried the work-around that you pointed me to (turning off the Beta checkbox was the only thing I needed to do)
Then it worked. GREAT!!! Thanks for helping me to find the right direction.
A few notes/questions:
1. running the .tcl script does not generate the .xsa file, I had to do a final step (File -> Export -> Export Hardware -> ...). Is that normal? Then is shall be in the readme.txt file.
2. there are still some warnings in the Tcl Console, is that normal? Do you see them also? I will list them below.
3. maybe the combination Windows 11 and Xilinx 2020 is not optimal. At a certain point in time I think it is better to switch to the latest version of Xilinx and the board files or the version just befor the latest. What is your opinion?
Here are the warnings in the TCL console:
WARNING: [Vivado 12-818] No files matched 'xdc/Zybo-Z7-Master.xdc'
WARNING: [Vivado 12-818] No files matched 'xdc/Zybo-Z7-Master.xdc'
CRITICAL WARNING: [PSU-1] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.050 . PS DDR interfaces might fail when entering negative DQS skew values.
CRITICAL WARNING: [PSU-2] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.044 . PS DDR interfaces might fail when entering negative DQS skew values.
CRITICAL WARNING: [PSU-3] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 has negative value -0.035 . PS DDR interfaces might fail when entering negative DQS skew values.
CRITICAL WARNING: [PSU-4] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 has negative value -0.100 . PS DDR interfaces might fail when entering negative DQS skew values.
CRITICAL WARNING: [PSU-1] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.050 . PS DDR interfaces might fail when entering negative DQS skew values.
CRITICAL WARNING: [PSU-2] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.044 . PS DDR interfaces might fail when entering negative DQS skew values.
CRITICAL WARNING: [PSU-3] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 has negative value -0.035 . PS DDR interfaces might fail when entering negative DQS skew values.
CRITICAL WARNING: [PSU-4] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 has negative value -0.100 . PS DDR interfaces might fail when entering negative DQS skew values.
CRITICAL WARNING: [PSU-1] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.050 . PS DDR interfaces might fail when entering negative DQS skew values.
CRITICAL WARNING: [PSU-2] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.044 . PS DDR interfaces might fail when entering negative DQS skew values.
CRITICAL WARNING: [PSU-3] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 has negative value -0.035 . PS DDR interfaces might fail when entering negative DQS skew values.
CRITICAL WARNING: [PSU-4] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 has negative value -0.100 . PS DDR interfaces might fail when entering negative DQS skew values.
WARNING: [BD 41-927] Following properties on pin /xadc_wiz_0/s_axi_aclk have been updated from connected ip, but BD cell '/xadc_wiz_0' does not accept parameter changes, so they may not be synchronized with cell properties:
FREQ_HZ = 50000000
Please resolve any mismatches by directly setting properties on BD cell </xadc_wiz_0> to completely resolve these warnings.
WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'M_AXI_GP0'. A default connection has been created.
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'c:/AimaginProjects/Z7000/adc_demo/hardware_design/vivado_tcl/adc_demo/adc_demo.gen/sources_1/bd/design_1/ip/design_1_auto_pc_0/design_1_auto_pc_0_ooc.xdc'
WARNING: [Project 1-645] Board images not set in Hardware Platform.
Regards,
johan.
RE: Errors when generating .xsa file (adc_demo project) - Added by Shawn Sebastian Pulle (ฌอน) over 1 year ago
Hi Johan,
Thank you for the feedback.
1. It seems the final step of generating the xsa file is not mentioned in the readme file. We will include that in future releases.
2. Yes. We also see these warnings. The warning related to the xdc file should not normally be there. We will look into the cause of that warning.
The critical warnings are related to vivado. You can get further info here (https://forum.digilent.com/topic/21356-getting-warnings-while-creating-vivado-project-with-zynq-boards/)
3. Yes. We will update the version of vivado/xilinx to a stable up to date version at a certain point in time.
If you look at the link I shared earlier ( https://support.xilinx.com/s/question/0D52E00006hpkZlSAI/re-fails-to-load-include-zynq7-processing-system-ip-in-block-design?language=en_US) that user is using windows 10 (released in 2015) with vivado 2018.
Considering after 2 years (vivado 2020) the error is still present, chances are very small that updating vivado would fix the issue you were facing.
Best Regards,
Shawn
RE: Errors when generating .xsa file (adc_demo project) - Added by martin van beek over 1 year ago
Hi Johan,
You must put the TCL commands in the TCL console at the bottom of the screen, don't use the "Tools | Run TCL script..." command from the top menu bar.
When using the console at the bottom, everything is running without errors.
Best regards,
Martin.