HELPDESK_WJ (Waijung)

Hi Johan,

Thank you for the feedback. These changes to the tcl file will be implemented in a future release.
It is strange that no block design is being created with the second warning. In our testing it did not stop the block design.

Hello,

See below my logfiles. It might be a good idea that Aimagin creates a build / test PC with a clean installation of Vivado and the required board files to verify that the delivered software will work at their customers site.

This is the logfile when trying to build the hardware:

start_gui
cd C:/AimaginProjects/Zybo/Hardware_Z7000/i2c_demo
source i2c_demo.tcl

1. proc checkRequiredFiles { origin_dir} {
2. set status true
3. set files [list \
4. "C:/Aimagin/zynq7000_xilinx/Other-Board_Files/zyboz7_project/vivado/My_Zybo-Z7-Master.xdc" \
5. ]
6. foreach ifile $files {
7. if { ![file isfile $ifile] } {
8. puts " Could not find remote file $ifile "
9. set status false
10. }
11. }
13. return $status
14. }
15. set origin_dir "."
16. if { [info exists ::origin_dir_loc] } {
17. set origin_dir $::origin_dir_loc
18. }
19. set xil_proj_name "project_1"
20. if { [info exists ::user_project_name] } {
21. set xil_proj_name $::user_project_name
22. }
23. variable script_file
24. set script_file "i2c_demo.tcl"
25. proc print_help {} {
26. variable script_file
27. puts "\nDescription:"
28. puts "Recreate a Vivado project from this script. The created project will be"
29. puts "functionally equivalent to the original project for which this script was"
30. puts "generated. The script contains commands for creating a project, filesets,"
31. puts "runs, adding/importing sources and setting properties on various objects.\n"
32. puts "Syntax:"
33. puts "$script_file"
34. puts "$script_file -tclargs \[--origin_dir <path>\]"
35. puts "$script_file -tclargs \[--project_name <name>\]"
36. puts "$script_file -tclargs \[--help\]\n"
37. puts "Usage:"
38. puts "Name Description"
39. puts "-------------------------------------------------------------------------"
40. puts "\[--origin_dir <path>\] Determine source file paths wrt this path. Default"
41. puts " origin_dir path value is \".\", otherwise, the value"
42. puts " that was set with the \"-paths_relative_to\" switch"
43. puts " when this script was generated.\n"
44. puts "\[--project_name <name>\] Create project with the specified name. Default"
45. puts " name is the name of the project from where this"
46. puts " script was generated.\n"
47. puts "\[--help\] Print help information for this script"
48. puts "-------------------------------------------------------------------------\n"
49. exit 0
50. }
51. if { $::argc > 0 } {
52. for {set i 0} {$i < $::argc} {incr i} {
53. set option [string trim [lindex $::argv $i]]
54. switch regexp - $option {
55. "--origin_dir" { incr i; set origin_dir [lindex $::argv $i] }
56. "--project_name" { incr i; set xil_proj_name [lindex $::argv $i] }
57. "--help" { print_help }
58. default {
59. if { [regexp {^-} $option] } {
60. puts "ERROR: Unknown option '$option' specified, please type '$script_file -tclargs --help' for usage info.\n"
61. return 1
62. }
63. }
64. }
65. }
66. }
67. set orig_proj_dir "[file normalize "$origin_dir/project_1"]"
68. set validate_required 0
69. if { $validate_required } {
70. if { [checkRequiredFiles $origin_dir] } {
71. puts "Tcl file $script_file is valid. All files required for project creation is accesable. "
72. } else {
73. puts "Tcl file $script_file is not valid. Not all files required for project creation is accesable. "
74. return
75. }
76. }
77. create_project ${_xil_proj_name_} ./${_xil_proj_name_} -part xc7z020clg400-1
    INFO: [IP_Flow 19-234] Refreshing IP repositories
    INFO: [IP_Flow 19-1704] No user IP repositories specified
    INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2020.2/data/ip'.
    create_project: Time (s): cpu = 00:00:04 ; elapsed = 00:00:08 . Memory (MB): peak = 1119.531 ; gain = 0.000
78. set proj_dir [get_property directory [current_project]]
79. set obj [current_project]
80. set_property -name "board_part_repo_paths" -value "[file normalize "$origin_dir/../../../../../../Users/admin/AppData/Roaming/Xilinx/Vivado/2020.2/xhub/board_store/xilinx_board_store"]" -objects $obj
    WARNING: [Vivado 12-9135] Ignoring repo path (C:/Users/admin/AppData/Roaming/Xilinx/Vivado/2020.2/xhub/board_store/xilinx_board_store) because it contains no board files
81. set_property -name "board_part" -value "digilentinc.com:zybo-z7-20:part0:1.0" -objects $obj
82. set_property -name "default_lib" -value "xil_defaultlib" -objects $obj
83. set_property -name "enable_vhdl_2008" -value "1" -objects $obj
84. set_property -name "ip_cache_permissions" -value "read write" -objects $obj
85. set_property -name "ip_output_repo" -value "$proj_dir/${_xil_proj_name_}.cache/ip" -objects $obj
86. set_property -name "mem.enable_memory_map_generation" -value "1" -objects $obj
87. set_property -name "platform.board_id" -value "zybo-z7-20" -objects $obj
88. set_property -name "sim.central_dir" -value "$proj_dir/${_xil_proj_name_}.ip_user_files" -objects $obj
89. set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj
90. set_property -name "simulator_language" -value "Mixed" -objects $obj
91. set_property -name "target_language" -value "VHDL" -objects $obj
92. if {[string equal [get_filesets -quiet sources_1] ""]} {
93. create_fileset -srcset sources_1
94. }
95. set obj [get_filesets sources_1]
96. set obj [get_filesets sources_1]
97. set_property -name "top" -value "design_1_wrapper" -objects $obj
98. if {[string equal [get_filesets -quiet constrs_1] ""]} {
99. create_fileset -constrset constrs_1
100. }
101. set obj [get_filesets constrs_1]
102. set file "[file normalize "$origin_dir/../My_Zybo-Z7-Master.xdc"]"
     ERROR: [Vivado 12-172] File or Directory 'C:/AimaginProjects/Zybo/Hardware_Z7000/My_Zybo-Z7-Master.xdc' does not exist

After copying the file My_Zybo-Z7-Master.xdc to a location two levels up in the directory tree this is the result (no block design is created):

source i2c_demo.tcl

1. proc checkRequiredFiles { origin_dir} {
2. set status true
3. set files [list \
4. "C:/Aimagin/zynq7000_xilinx/Other-Board_Files/zyboz7_project/vivado/My_Zybo-Z7-Master.xdc" \
5. ]
6. foreach ifile $files {
7. if { ![file isfile $ifile] } {
8. puts " Could not find remote file $ifile "
9. set status false
10. }
11. }
13. return $status
14. }
15. set origin_dir "."
16. if { [info exists ::origin_dir_loc] } {
17. set origin_dir $::origin_dir_loc
18. }
19. set xil_proj_name "project_1"
20. if { [info exists ::user_project_name] } {
21. set xil_proj_name $::user_project_name
22. }
23. variable script_file
24. set script_file "i2c_demo.tcl"
25. proc print_help {} {
26. variable script_file
27. puts "\nDescription:"
28. puts "Recreate a Vivado project from this script. The created project will be"
29. puts "functionally equivalent to the original project for which this script was"
30. puts "generated. The script contains commands for creating a project, filesets,"
31. puts "runs, adding/importing sources and setting properties on various objects.\n"
32. puts "Syntax:"
33. puts "$script_file"
34. puts "$script_file -tclargs \[--origin_dir <path>\]"
35. puts "$script_file -tclargs \[--project_name <name>\]"
36. puts "$script_file -tclargs \[--help\]\n"
37. puts "Usage:"
38. puts "Name Description"
39. puts "-------------------------------------------------------------------------"
40. puts "\[--origin_dir <path>\] Determine source file paths wrt this path. Default"
41. puts " origin_dir path value is \".\", otherwise, the value"
42. puts " that was set with the \"-paths_relative_to\" switch"
43. puts " when this script was generated.\n"
44. puts "\[--project_name <name>\] Create project with the specified name. Default"
45. puts " name is the name of the project from where this"
46. puts " script was generated.\n"
47. puts "\[--help\] Print help information for this script"
48. puts "-------------------------------------------------------------------------\n"
49. exit 0
50. }
51. if { $::argc > 0 } {
52. for {set i 0} {$i < $::argc} {incr i} {
53. set option [string trim [lindex $::argv $i]]
54. switch regexp - $option {
55. "--origin_dir" { incr i; set origin_dir [lindex $::argv $i] }
56. "--project_name" { incr i; set xil_proj_name [lindex $::argv $i] }
57. "--help" { print_help }
58. default {
59. if { [regexp {^-} $option] } {
60. puts "ERROR: Unknown option '$option' specified, please type '$script_file -tclargs --help' for usage info.\n"
61. return 1
62. }
63. }
64. }
65. }
66. }
67. set orig_proj_dir "[file normalize "$origin_dir/project_1"]"
68. set validate_required 0
69. if { $validate_required } {
70. if { [checkRequiredFiles $origin_dir] } {
71. puts "Tcl file $script_file is valid. All files required for project creation is accesable. "
72. } else {
73. puts "Tcl file $script_file is not valid. Not all files required for project creation is accesable. "
74. return
75. }
76. }
77. create_project ${_xil_proj_name_} ./${_xil_proj_name_} -part xc7z020clg400-1
    INFO: [IP_Flow 19-234] Refreshing IP repositories
    INFO: [IP_Flow 19-1704] No user IP repositories specified
    INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2020.2/data/ip'.
78. set proj_dir [get_property directory [current_project]]
79. set obj [current_project]
80. set_property -name "board_part_repo_paths" -value "[file normalize "$origin_dir/../../../../../../Users/admin/AppData/Roaming/Xilinx/Vivado/2020.2/xhub/board_store/xilinx_board_store"]" -objects $obj
    WARNING: [Vivado 12-9135] Ignoring repo path (C:/Users/admin/AppData/Roaming/Xilinx/Vivado/2020.2/xhub/board_store/xilinx_board_store) because it contains no board files
81. set_property -name "board_part" -value "digilentinc.com:zybo-z7-20:part0:1.0" -objects $obj
82. set_property -name "default_lib" -value "xil_defaultlib" -objects $obj
83. set_property -name "enable_vhdl_2008" -value "1" -objects $obj
84. set_property -name "ip_cache_permissions" -value "read write" -objects $obj
85. set_property -name "ip_output_repo" -value "$proj_dir/${_xil_proj_name_}.cache/ip" -objects $obj
86. set_property -name "mem.enable_memory_map_generation" -value "1" -objects $obj
87. set_property -name "platform.board_id" -value "zybo-z7-20" -objects $obj
88. set_property -name "sim.central_dir" -value "$proj_dir/${_xil_proj_name_}.ip_user_files" -objects $obj
89. set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj
90. set_property -name "simulator_language" -value "Mixed" -objects $obj
91. set_property -name "target_language" -value "VHDL" -objects $obj
92. if {[string equal [get_filesets -quiet sources_1] ""]} {
93. create_fileset -srcset sources_1
94. }
95. set obj [get_filesets sources_1]
96. set obj [get_filesets sources_1]
97. set_property -name "top" -value "design_1_wrapper" -objects $obj
98. if {[string equal [get_filesets -quiet constrs_1] ""]} {
99. create_fileset -constrset constrs_1
100. }
101. set obj [get_filesets constrs_1]
102. set file "[file normalize "$origin_dir/../My_Zybo-Z7-Master.xdc"]"
103. set file_added [add_files -norecurse -fileset $obj [list $file]]
104. set file "$origin_dir/../My_Zybo-Z7-Master.xdc"
105. set file [file normalize $file]
106. set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]]
107. set_property -name "file_type" -value "XDC" -objects $file_obj
108. set obj [get_filesets constrs_1]
109. if {[string equal [get_filesets -quiet sim_1] ""]} {
110. create_fileset -simset sim_1
111. }
112. set obj [get_filesets sim_1]
113. set obj [get_filesets sim_1]
114. set_property -name "hbs.configure_design_for_hier_access" -value "1" -objects $obj
115. set_property -name "top" -value "design_1_wrapper" -objects $obj
116. set_property -name "top_lib" -value "xil_defaultlib" -objects $obj
117. set obj [get_filesets utils_1]
118. set obj [get_filesets utils_1]
119. proc cr_bd_design_1 { parentCell } {
121. # CHANGE DESIGN NAME HERE
122. set design_name design_1
124. common::send_gid_msg -ssname BD::TCL -id 2010 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..."
126. create_bd_design $design_name
128. set bCheckIPsPassed 1
129. ##################################################################
130. # CHECK IPs
131. ##################################################################
132. set bCheckIPs 1
133. if { $bCheckIPs == 1 } {
134. set list_check_ips "\
135. xilinx.com:ip:processing_system7:5.5\
136. "
138. set list_ips_missing ""
139. common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
141. foreach ip_vlnv $list_check_ips {
142. set ip_obj [get_ipdefs -all $ip_vlnv]
143. if { $ip_obj eq "" } {
144. lappend list_ips_missing $ip_vlnv
145. }
146. }
148. if { $list_ips_missing ne "" } {
149. catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP to the project." }
150. set bCheckIPsPassed 0
151. }
153. }
155. if { $bCheckIPsPassed != 1 } {
156. common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above."
157. return 3
158. }
160. variable script_folder
162. if { $parentCell eq "" } {
163. set parentCell [get_bd_cells /]
164. }
166. # Get object for parentCell
167. set parentObj [get_bd_cells $parentCell]
168. if { $parentObj == "" } {
169. catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
170. return
171. }
173. # Make sure parentObj is hier blk
174. set parentType [get_property TYPE $parentObj]
175. if { $parentType ne "hier" } {
176. catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
177. return
178. }
180. # Save current instance; Restore later
181. set oldCurInst [current_bd_instance .]
183. # Set parent object as current
184. current_bd_instance $parentObj
187. # Create interface ports
188. set DDR [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR ]
190. set FIXED_IO [ create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 FIXED_IO ]
192. set GPIO_0_0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 GPIO_0_0 ]
195. # Create ports
197. # Create instance: processing_system7_0, and set properties
198. set processing_system7_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0 ]
199. set_property -dict [ list \
200. CONFIG.PCW_ACT_APU_PERIPHERAL_FREQMHZ {666.666687} \
201. CONFIG.PCW_ACT_CAN_PERIPHERAL_FREQMHZ {10.000000} \
202. CONFIG.PCW_ACT_DCI_PERIPHERAL_FREQMHZ {10.158730} \
203. CONFIG.PCW_ACT_ENET0_PERIPHERAL_FREQMHZ {125.000000} \
204. CONFIG.PCW_ACT_ENET1_PERIPHERAL_FREQMHZ {10.000000} \
205. CONFIG.PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ {50.000000} \
206. CONFIG.PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ {10.000000} \
207. CONFIG.PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ {10.000000} \
208. CONFIG.PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ {10.000000} \
209. CONFIG.PCW_ACT_PCAP_PERIPHERAL_FREQMHZ {200.000000} \
210. CONFIG.PCW_ACT_QSPI_PERIPHERAL_FREQMHZ {200.000000} \
211. CONFIG.PCW_ACT_SDIO_PERIPHERAL_FREQMHZ {10.000000} \
212. CONFIG.PCW_ACT_SMC_PERIPHERAL_FREQMHZ {10.000000} \
213. CONFIG.PCW_ACT_SPI_PERIPHERAL_FREQMHZ {10.000000} \
214. CONFIG.PCW_ACT_TPIU_PERIPHERAL_FREQMHZ {200.000000} \
215. CONFIG.PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ {111.111115} \
216. CONFIG.PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ {111.111115} \
217. CONFIG.PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ {111.111115} \
218. CONFIG.PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ {111.111115} \
219. CONFIG.PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ {111.111115} \
220. CONFIG.PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ {111.111115} \
221. CONFIG.PCW_ACT_UART_PERIPHERAL_FREQMHZ {100.000000} \
222. CONFIG.PCW_ACT_WDT_PERIPHERAL_FREQMHZ {111.111115} \
223. CONFIG.PCW_APU_CLK_RATIO_ENABLE {6:2:1} \
224. CONFIG.PCW_APU_PERIPHERAL_FREQMHZ {667} \
225. CONFIG.PCW_ARMPLL_CTRL_FBDIV {40} \
226. CONFIG.PCW_CAN_PERIPHERAL_DIVISOR0 {1} \
227. CONFIG.PCW_CAN_PERIPHERAL_DIVISOR1 {1} \
228. CONFIG.PCW_CLK0_FREQ {50000000} \
229. CONFIG.PCW_CLK1_FREQ {10000000} \
230. CONFIG.PCW_CLK2_FREQ {10000000} \
231. CONFIG.PCW_CLK3_FREQ {10000000} \
232. CONFIG.PCW_CPU_CPU_6X4X_MAX_RANGE {667} \
233. CONFIG.PCW_CPU_CPU_PLL_FREQMHZ {1333.333} \
234. CONFIG.PCW_CPU_PERIPHERAL_CLKSRC {ARM PLL} \
235. CONFIG.PCW_CPU_PERIPHERAL_DIVISOR0 {2} \
236. CONFIG.PCW_CRYSTAL_PERIPHERAL_FREQMHZ {33.333333} \
237. CONFIG.PCW_DCI_PERIPHERAL_CLKSRC {DDR PLL} \
238. CONFIG.PCW_DCI_PERIPHERAL_DIVISOR0 {15} \
239. CONFIG.PCW_DCI_PERIPHERAL_DIVISOR1 {7} \
240. CONFIG.PCW_DCI_PERIPHERAL_FREQMHZ {10.159} \
241. CONFIG.PCW_DDRPLL_CTRL_FBDIV {32} \
242. CONFIG.PCW_DDR_DDR_PLL_FREQMHZ {1066.667} \
243. CONFIG.PCW_DDR_HPRLPR_QUEUE_PARTITION {HPR/LPR} \
244. CONFIG.PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL {15} \
245. CONFIG.PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL {2} \
246. CONFIG.PCW_DDR_PERIPHERAL_CLKSRC {DDR PLL} \
247. CONFIG.PCW_DDR_PERIPHERAL_DIVISOR0 {2} \
248. CONFIG.PCW_DDR_PORT0_HPR_ENABLE {0} \
249. CONFIG.PCW_DDR_PORT1_HPR_ENABLE {0} \
250. CONFIG.PCW_DDR_PORT2_HPR_ENABLE {0} \
251. CONFIG.PCW_DDR_PORT3_HPR_ENABLE {0} \
252. CONFIG.PCW_DDR_RAM_HIGHADDR {0x3FFFFFFF} \
253. CONFIG.PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL {2} \
254. CONFIG.PCW_ENET0_ENET0_IO {MIO 16 .. 27} \
255. CONFIG.PCW_ENET0_GRP_MDIO_ENABLE {1} \
256. CONFIG.PCW_ENET0_GRP_MDIO_IO {MIO 52 .. 53} \
257. CONFIG.PCW_ENET0_PERIPHERAL_CLKSRC {IO PLL} \
258. CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR0 {8} \
259. CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR1 {1} \
260. CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {1} \
261. CONFIG.PCW_ENET0_PERIPHERAL_FREQMHZ {1000 Mbps} \
262. CONFIG.PCW_ENET0_RESET_ENABLE {0} \
263. CONFIG.PCW_ENET1_GRP_MDIO_ENABLE {0} \
264. CONFIG.PCW_ENET1_PERIPHERAL_CLKSRC {IO PLL} \
265. CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR0 {1} \
266. CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR1 {1} \
267. CONFIG.PCW_ENET1_PERIPHERAL_ENABLE {0} \
268. CONFIG.PCW_ENET1_PERIPHERAL_FREQMHZ {1000 Mbps} \
269. CONFIG.PCW_ENET1_RESET_ENABLE {0} \
270. CONFIG.PCW_ENET_RESET_ENABLE {1} \
271. CONFIG.PCW_ENET_RESET_POLARITY {Active Low} \
272. CONFIG.PCW_ENET_RESET_SELECT {Share reset pin} \
273. CONFIG.PCW_EN_4K_TIMER {0} \
274. CONFIG.PCW_EN_EMIO_ENET0 {0} \
275. CONFIG.PCW_EN_EMIO_GPIO {1} \
276. CONFIG.PCW_EN_EMIO_I2C0 {0} \
277. CONFIG.PCW_EN_EMIO_I2C1 {0} \
278. CONFIG.PCW_EN_ENET0 {1} \
279. CONFIG.PCW_EN_GPIO {1} \
280. CONFIG.PCW_EN_I2C0 {1} \
281. CONFIG.PCW_EN_I2C1 {1} \
282. CONFIG.PCW_EN_QSPI {1} \
283. CONFIG.PCW_EN_SDIO0 {0} \
284. CONFIG.PCW_EN_UART1 {1} \
285. CONFIG.PCW_EN_USB0 {0} \
286. CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR0 {5} \
287. CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR1 {4} \
288. CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR0 {1} \
289. CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR1 {1} \
290. CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR0 {1} \
291. CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR1 {1} \
292. CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR0 {1} \
293. CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR1 {1} \
294. CONFIG.PCW_FPGA_FCLK0_ENABLE {1} \
295. CONFIG.PCW_FPGA_FCLK1_ENABLE {0} \
296. CONFIG.PCW_FPGA_FCLK2_ENABLE {0} \
297. CONFIG.PCW_FPGA_FCLK3_ENABLE {0} \
298. CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {1} \
299. CONFIG.PCW_GPIO_EMIO_GPIO_IO {26} \
300. CONFIG.PCW_GPIO_EMIO_GPIO_WIDTH {26} \
301. CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1} \
302. CONFIG.PCW_GPIO_MIO_GPIO_IO {MIO} \
303. CONFIG.PCW_GPIO_PERIPHERAL_ENABLE {0} \
304. CONFIG.PCW_I2C0_GRP_INT_ENABLE {1} \
305. CONFIG.PCW_I2C0_GRP_INT_IO {EMIO} \
306. CONFIG.PCW_I2C0_I2C0_IO {MIO 14 .. 15} \
307. CONFIG.PCW_I2C0_PERIPHERAL_ENABLE {1} \
308. CONFIG.PCW_I2C0_RESET_ENABLE {0} \
309. CONFIG.PCW_I2C1_GRP_INT_ENABLE {1} \
310. CONFIG.PCW_I2C1_GRP_INT_IO {EMIO} \
311. CONFIG.PCW_I2C1_I2C1_IO {MIO 12 .. 13} \
312. CONFIG.PCW_I2C1_PERIPHERAL_ENABLE {1} \
313. CONFIG.PCW_I2C1_RESET_ENABLE {0} \
314. CONFIG.PCW_I2C_PERIPHERAL_FREQMHZ {111.111115} \
315. CONFIG.PCW_I2C_RESET_ENABLE {1} \
316. CONFIG.PCW_I2C_RESET_SELECT {Share reset pin} \
317. CONFIG.PCW_IOPLL_CTRL_FBDIV {30} \
318. CONFIG.PCW_IO_IO_PLL_FREQMHZ {1000.000} \
319. CONFIG.PCW_IRQ_F2P_MODE {DIRECT} \
320. CONFIG.PCW_MIO_0_DIRECTION {inout} \
321. CONFIG.PCW_MIO_0_IOTYPE {LVCMOS 3.3V} \
322. CONFIG.PCW_MIO_0_PULLUP {enabled} \
323. CONFIG.PCW_MIO_0_SLEW {slow} \
324. CONFIG.PCW_MIO_10_DIRECTION {inout} \
325. CONFIG.PCW_MIO_10_IOTYPE {LVCMOS 3.3V} \
326. CONFIG.PCW_MIO_10_PULLUP {enabled} \
327. CONFIG.PCW_MIO_10_SLEW {slow} \
328. CONFIG.PCW_MIO_11_DIRECTION {inout} \
329. CONFIG.PCW_MIO_11_IOTYPE {LVCMOS 3.3V} \
330. CONFIG.PCW_MIO_11_PULLUP {enabled} \
331. CONFIG.PCW_MIO_11_SLEW {slow} \
332. CONFIG.PCW_MIO_12_DIRECTION {inout} \
333. CONFIG.PCW_MIO_12_IOTYPE {LVCMOS 3.3V} \
334. CONFIG.PCW_MIO_12_PULLUP {enabled} \
335. CONFIG.PCW_MIO_12_SLEW {slow} \
336. CONFIG.PCW_MIO_13_DIRECTION {inout} \
337. CONFIG.PCW_MIO_13_IOTYPE {LVCMOS 3.3V} \
338. CONFIG.PCW_MIO_13_PULLUP {enabled} \
339. CONFIG.PCW_MIO_13_SLEW {slow} \
340. CONFIG.PCW_MIO_14_DIRECTION {inout} \
341. CONFIG.PCW_MIO_14_IOTYPE {LVCMOS 3.3V} \
342. CONFIG.PCW_MIO_14_PULLUP {enabled} \
343. CONFIG.PCW_MIO_14_SLEW {slow} \
344. CONFIG.PCW_MIO_15_DIRECTION {inout} \
345. CONFIG.PCW_MIO_15_IOTYPE {LVCMOS 3.3V} \
346. CONFIG.PCW_MIO_15_PULLUP {enabled} \
347. CONFIG.PCW_MIO_15_SLEW {slow} \
348. CONFIG.PCW_MIO_16_DIRECTION {out} \
349. CONFIG.PCW_MIO_16_IOTYPE {LVCMOS 1.8V} \
350. CONFIG.PCW_MIO_16_PULLUP {enabled} \
351. CONFIG.PCW_MIO_16_SLEW {fast} \
352. CONFIG.PCW_MIO_17_DIRECTION {out} \
353. CONFIG.PCW_MIO_17_IOTYPE {LVCMOS 1.8V} \
354. CONFIG.PCW_MIO_17_PULLUP {enabled} \
355. CONFIG.PCW_MIO_17_SLEW {fast} \
356. CONFIG.PCW_MIO_18_DIRECTION {out} \
357. CONFIG.PCW_MIO_18_IOTYPE {LVCMOS 1.8V} \
358. CONFIG.PCW_MIO_18_PULLUP {enabled} \
359. CONFIG.PCW_MIO_18_SLEW {fast} \
360. CONFIG.PCW_MIO_19_DIRECTION {out} \
361. CONFIG.PCW_MIO_19_IOTYPE {LVCMOS 1.8V} \
362. CONFIG.PCW_MIO_19_PULLUP {enabled} \
363. CONFIG.PCW_MIO_19_SLEW {fast} \
364. CONFIG.PCW_MIO_1_DIRECTION {out} \
365. CONFIG.PCW_MIO_1_IOTYPE {LVCMOS 3.3V} \
366. CONFIG.PCW_MIO_1_PULLUP {enabled} \
367. CONFIG.PCW_MIO_1_SLEW {slow} \
368. CONFIG.PCW_MIO_20_DIRECTION {out} \
369. CONFIG.PCW_MIO_20_IOTYPE {LVCMOS 1.8V} \
370. CONFIG.PCW_MIO_20_PULLUP {enabled} \
371. CONFIG.PCW_MIO_20_SLEW {fast} \
372. CONFIG.PCW_MIO_21_DIRECTION {out} \
373. CONFIG.PCW_MIO_21_IOTYPE {LVCMOS 1.8V} \
374. CONFIG.PCW_MIO_21_PULLUP {enabled} \
375. CONFIG.PCW_MIO_21_SLEW {fast} \
376. CONFIG.PCW_MIO_22_DIRECTION {in} \
377. CONFIG.PCW_MIO_22_IOTYPE {LVCMOS 1.8V} \
378. CONFIG.PCW_MIO_22_PULLUP {enabled} \
379. CONFIG.PCW_MIO_22_SLEW {fast} \
380. CONFIG.PCW_MIO_23_DIRECTION {in} \
381. CONFIG.PCW_MIO_23_IOTYPE {LVCMOS 1.8V} \
382. CONFIG.PCW_MIO_23_PULLUP {enabled} \
383. CONFIG.PCW_MIO_23_SLEW {fast} \
384. CONFIG.PCW_MIO_24_DIRECTION {in} \
385. CONFIG.PCW_MIO_24_IOTYPE {LVCMOS 1.8V} \
386. CONFIG.PCW_MIO_24_PULLUP {enabled} \
387. CONFIG.PCW_MIO_24_SLEW {fast} \
388. CONFIG.PCW_MIO_25_DIRECTION {in} \
389. CONFIG.PCW_MIO_25_IOTYPE {LVCMOS 1.8V} \
390. CONFIG.PCW_MIO_25_PULLUP {enabled} \
391. CONFIG.PCW_MIO_25_SLEW {fast} \
392. CONFIG.PCW_MIO_26_DIRECTION {in} \
393. CONFIG.PCW_MIO_26_IOTYPE {LVCMOS 1.8V} \
394. CONFIG.PCW_MIO_26_PULLUP {enabled} \
395. CONFIG.PCW_MIO_26_SLEW {fast} \
396. CONFIG.PCW_MIO_27_DIRECTION {in} \
397. CONFIG.PCW_MIO_27_IOTYPE {LVCMOS 1.8V} \
398. CONFIG.PCW_MIO_27_PULLUP {enabled} \
399. CONFIG.PCW_MIO_27_SLEW {fast} \
400. CONFIG.PCW_MIO_28_DIRECTION {inout} \
401. CONFIG.PCW_MIO_28_IOTYPE {LVCMOS 1.8V} \
402. CONFIG.PCW_MIO_28_PULLUP {enabled} \
403. CONFIG.PCW_MIO_28_SLEW {fast} \
404. CONFIG.PCW_MIO_29_DIRECTION {inout} \
405. CONFIG.PCW_MIO_29_IOTYPE {LVCMOS 1.8V} \
406. CONFIG.PCW_MIO_29_PULLUP {enabled} \
407. CONFIG.PCW_MIO_29_SLEW {fast} \
408. CONFIG.PCW_MIO_2_DIRECTION {inout} \
409. CONFIG.PCW_MIO_2_IOTYPE {LVCMOS 3.3V} \
410. CONFIG.PCW_MIO_2_PULLUP {disabled} \
411. CONFIG.PCW_MIO_2_SLEW {slow} \
412. CONFIG.PCW_MIO_30_DIRECTION {inout} \
413. CONFIG.PCW_MIO_30_IOTYPE {LVCMOS 1.8V} \
414. CONFIG.PCW_MIO_30_PULLUP {enabled} \
415. CONFIG.PCW_MIO_30_SLEW {fast} \
416. CONFIG.PCW_MIO_31_DIRECTION {inout} \
417. CONFIG.PCW_MIO_31_IOTYPE {LVCMOS 1.8V} \
418. CONFIG.PCW_MIO_31_PULLUP {enabled} \
419. CONFIG.PCW_MIO_31_SLEW {fast} \
420. CONFIG.PCW_MIO_32_DIRECTION {inout} \
421. CONFIG.PCW_MIO_32_IOTYPE {LVCMOS 1.8V} \
422. CONFIG.PCW_MIO_32_PULLUP {enabled} \
423. CONFIG.PCW_MIO_32_SLEW {fast} \
424. CONFIG.PCW_MIO_33_DIRECTION {inout} \
425. CONFIG.PCW_MIO_33_IOTYPE {LVCMOS 1.8V} \
426. CONFIG.PCW_MIO_33_PULLUP {enabled} \
427. CONFIG.PCW_MIO_33_SLEW {fast} \
428. CONFIG.PCW_MIO_34_DIRECTION {inout} \
429. CONFIG.PCW_MIO_34_IOTYPE {LVCMOS 1.8V} \
430. CONFIG.PCW_MIO_34_PULLUP {enabled} \
431. CONFIG.PCW_MIO_34_SLEW {fast} \
432. CONFIG.PCW_MIO_35_DIRECTION {inout} \
433. CONFIG.PCW_MIO_35_IOTYPE {LVCMOS 1.8V} \
434. CONFIG.PCW_MIO_35_PULLUP {enabled} \
435. CONFIG.PCW_MIO_35_SLEW {fast} \
436. CONFIG.PCW_MIO_36_DIRECTION {inout} \
437. CONFIG.PCW_MIO_36_IOTYPE {LVCMOS 1.8V} \
438. CONFIG.PCW_MIO_36_PULLUP {enabled} \
439. CONFIG.PCW_MIO_36_SLEW {fast} \
440. CONFIG.PCW_MIO_37_DIRECTION {inout} \
441. CONFIG.PCW_MIO_37_IOTYPE {LVCMOS 1.8V} \
442. CONFIG.PCW_MIO_37_PULLUP {enabled} \
443. CONFIG.PCW_MIO_37_SLEW {fast} \
444. CONFIG.PCW_MIO_38_DIRECTION {inout} \
445. CONFIG.PCW_MIO_38_IOTYPE {LVCMOS 1.8V} \
446. CONFIG.PCW_MIO_38_PULLUP {enabled} \
447. CONFIG.PCW_MIO_38_SLEW {fast} \
448. CONFIG.PCW_MIO_39_DIRECTION {inout} \
449. CONFIG.PCW_MIO_39_IOTYPE {LVCMOS 1.8V} \
450. CONFIG.PCW_MIO_39_PULLUP {enabled} \
451. CONFIG.PCW_MIO_39_SLEW {fast} \
452. CONFIG.PCW_MIO_3_DIRECTION {inout} \
453. CONFIG.PCW_MIO_3_IOTYPE {LVCMOS 3.3V} \
454. CONFIG.PCW_MIO_3_PULLUP {disabled} \
455. CONFIG.PCW_MIO_3_SLEW {slow} \
456. CONFIG.PCW_MIO_40_DIRECTION {inout} \
457. CONFIG.PCW_MIO_40_IOTYPE {LVCMOS 1.8V} \
458. CONFIG.PCW_MIO_40_PULLUP {enabled} \
459. CONFIG.PCW_MIO_40_SLEW {slow} \
460. CONFIG.PCW_MIO_41_DIRECTION {inout} \
461. CONFIG.PCW_MIO_41_IOTYPE {LVCMOS 1.8V} \
462. CONFIG.PCW_MIO_41_PULLUP {enabled} \
463. CONFIG.PCW_MIO_41_SLEW {slow} \
464. CONFIG.PCW_MIO_42_DIRECTION {inout} \
465. CONFIG.PCW_MIO_42_IOTYPE {LVCMOS 1.8V} \
466. CONFIG.PCW_MIO_42_PULLUP {enabled} \
467. CONFIG.PCW_MIO_42_SLEW {slow} \
468. CONFIG.PCW_MIO_43_DIRECTION {inout} \
469. CONFIG.PCW_MIO_43_IOTYPE {LVCMOS 1.8V} \
470. CONFIG.PCW_MIO_43_PULLUP {enabled} \
471. CONFIG.PCW_MIO_43_SLEW {slow} \
472. CONFIG.PCW_MIO_44_DIRECTION {inout} \
473. CONFIG.PCW_MIO_44_IOTYPE {LVCMOS 1.8V} \
474. CONFIG.PCW_MIO_44_PULLUP {enabled} \
475. CONFIG.PCW_MIO_44_SLEW {slow} \
476. CONFIG.PCW_MIO_45_DIRECTION {inout} \
477. CONFIG.PCW_MIO_45_IOTYPE {LVCMOS 1.8V} \
478. CONFIG.PCW_MIO_45_PULLUP {enabled} \
479. CONFIG.PCW_MIO_45_SLEW {slow} \
480. CONFIG.PCW_MIO_46_DIRECTION {out} \
481. CONFIG.PCW_MIO_46_IOTYPE {LVCMOS 1.8V} \
482. CONFIG.PCW_MIO_46_PULLUP {enabled} \
483. CONFIG.PCW_MIO_46_SLEW {slow} \
484. CONFIG.PCW_MIO_47_DIRECTION {in} \
485. CONFIG.PCW_MIO_47_IOTYPE {LVCMOS 1.8V} \
486. CONFIG.PCW_MIO_47_PULLUP {enabled} \
487. CONFIG.PCW_MIO_47_SLEW {slow} \
488. CONFIG.PCW_MIO_48_DIRECTION {out} \
489. CONFIG.PCW_MIO_48_IOTYPE {LVCMOS 1.8V} \
490. CONFIG.PCW_MIO_48_PULLUP {enabled} \
491. CONFIG.PCW_MIO_48_SLEW {slow} \
492. CONFIG.PCW_MIO_49_DIRECTION {in} \
493. CONFIG.PCW_MIO_49_IOTYPE {LVCMOS 1.8V} \
494. CONFIG.PCW_MIO_49_PULLUP {enabled} \
495. CONFIG.PCW_MIO_49_SLEW {slow} \
496. CONFIG.PCW_MIO_4_DIRECTION {inout} \
497. CONFIG.PCW_MIO_4_IOTYPE {LVCMOS 3.3V} \
498. CONFIG.PCW_MIO_4_PULLUP {disabled} \
499. CONFIG.PCW_MIO_4_SLEW {slow} \
500. CONFIG.PCW_MIO_50_DIRECTION {inout} \
501. CONFIG.PCW_MIO_50_IOTYPE {LVCMOS 1.8V} \
502. CONFIG.PCW_MIO_50_PULLUP {enabled} \
503. CONFIG.PCW_MIO_50_SLEW {slow} \
504. CONFIG.PCW_MIO_51_DIRECTION {inout} \
505. CONFIG.PCW_MIO_51_IOTYPE {LVCMOS 1.8V} \
506. CONFIG.PCW_MIO_51_PULLUP {enabled} \
507. CONFIG.PCW_MIO_51_SLEW {slow} \
508. CONFIG.PCW_MIO_52_DIRECTION {out} \
509. CONFIG.PCW_MIO_52_IOTYPE {LVCMOS 1.8V} \
510. CONFIG.PCW_MIO_52_PULLUP {enabled} \
511. CONFIG.PCW_MIO_52_SLEW {slow} \
512. CONFIG.PCW_MIO_53_DIRECTION {inout} \
513. CONFIG.PCW_MIO_53_IOTYPE {LVCMOS 1.8V} \
514. CONFIG.PCW_MIO_53_PULLUP {enabled} \
515. CONFIG.PCW_MIO_53_SLEW {slow} \
516. CONFIG.PCW_MIO_5_DIRECTION {inout} \
517. CONFIG.PCW_MIO_5_IOTYPE {LVCMOS 3.3V} \
518. CONFIG.PCW_MIO_5_PULLUP {disabled} \
519. CONFIG.PCW_MIO_5_SLEW {slow} \
520. CONFIG.PCW_MIO_6_DIRECTION {out} \
521. CONFIG.PCW_MIO_6_IOTYPE {LVCMOS 3.3V} \
522. CONFIG.PCW_MIO_6_PULLUP {disabled} \
523. CONFIG.PCW_MIO_6_SLEW {slow} \
524. CONFIG.PCW_MIO_7_DIRECTION {out} \
525. CONFIG.PCW_MIO_7_IOTYPE {LVCMOS 3.3V} \
526. CONFIG.PCW_MIO_7_PULLUP {disabled} \
527. CONFIG.PCW_MIO_7_SLEW {slow} \
528. CONFIG.PCW_MIO_8_DIRECTION {out} \
529. CONFIG.PCW_MIO_8_IOTYPE {LVCMOS 3.3V} \
530. CONFIG.PCW_MIO_8_PULLUP {disabled} \
531. CONFIG.PCW_MIO_8_SLEW {slow} \
532. CONFIG.PCW_MIO_9_DIRECTION {inout} \
533. CONFIG.PCW_MIO_9_IOTYPE {LVCMOS 3.3V} \
534. CONFIG.PCW_MIO_9_PULLUP {enabled} \
535. CONFIG.PCW_MIO_9_SLEW {slow} \
536. CONFIG.PCW_MIO_TREE_PERIPHERALS {GPIO#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#GPIO#Quad SPI Flash#GPIO#GPIO#GPIO#I2C 1#I2C 1#I2C 0#I2C 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#UART 1#UART 1#GPIO#GPIO#Enet 0#Enet 0} \
537. CONFIG.PCW_MIO_TREE_SIGNALS {gpio⁰#qspi0_ss_b#qspi0_io⁰#qspi0_io¹#qspi0_io²#qspi0_io³/HOLD_B#qspi0_sclk#gpio⁷#qspi_fbclk#gpio⁹#gpio¹⁰#gpio¹¹#scl#sda#scl#sda#tx_clk#txd⁰#txd¹#txd²#txd³#tx_ctl#rx_clk#rxd⁰#rxd¹#rxd²#rxd³#rx_ctl#gpio²⁸#gpio²⁹#gpio³⁰#gpio³¹#gpio³²#gpio³³#gpio³⁴#gpio³⁵#gpio³⁶#gpio³⁷#gpio³⁸#gpio³⁹#gpio⁴⁰#gpio⁴¹#gpio⁴²#gpio⁴³#gpio⁴⁴#gpio⁴⁵#gpio⁴⁶#gpio⁴⁷#tx#rx#gpio⁵⁰#gpio⁵¹#mdc#mdio} \
538. CONFIG.PCW_NAND_GRP_D8_ENABLE {0} \
539. CONFIG.PCW_NAND_PERIPHERAL_ENABLE {0} \
540. CONFIG.PCW_NOR_GRP_A25_ENABLE {0} \
541. CONFIG.PCW_NOR_GRP_CS0_ENABLE {0} \
542. CONFIG.PCW_NOR_GRP_CS1_ENABLE {0} \
543. CONFIG.PCW_NOR_GRP_SRAM_CS0_ENABLE {0} \
544. CONFIG.PCW_NOR_GRP_SRAM_CS1_ENABLE {0} \
545. CONFIG.PCW_NOR_GRP_SRAM_INT_ENABLE {0} \
546. CONFIG.PCW_NOR_PERIPHERAL_ENABLE {0} \
547. CONFIG.PCW_OVERRIDE_BASIC_CLOCK {0} \
548. CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY0 {0.221} \
549. CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY1 {0.222} \
550. CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY2 {0.217} \
551. CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY3 {0.244} \
552. CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_0 {-0.050} \
553. CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_1 {-0.044} \
554. CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_2 {-0.035} \
555. CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_3 {-0.100} \
556. CONFIG.PCW_PCAP_PERIPHERAL_CLKSRC {IO PLL} \
557. CONFIG.PCW_PCAP_PERIPHERAL_DIVISOR0 {5} \
558. CONFIG.PCW_PCAP_PERIPHERAL_FREQMHZ {200} \
559. CONFIG.PCW_PJTAG_PERIPHERAL_ENABLE {0} \
560. CONFIG.PCW_PLL_BYPASSMODE_ENABLE {0} \
561. CONFIG.PCW_PRESET_BANK0_VOLTAGE {LVCMOS 3.3V} \
562. CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 1.8V} \
563. CONFIG.PCW_QSPI_GRP_FBCLK_ENABLE {1} \
564. CONFIG.PCW_QSPI_GRP_FBCLK_IO {MIO 8} \
565. CONFIG.PCW_QSPI_GRP_IO1_ENABLE {0} \
566. CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE {1} \
567. CONFIG.PCW_QSPI_GRP_SINGLE_SS_IO {MIO 1 .. 6} \
568. CONFIG.PCW_QSPI_GRP_SS1_ENABLE {0} \
569. CONFIG.PCW_QSPI_INTERNAL_HIGHADDRESS {0xFCFFFFFF} \
570. CONFIG.PCW_QSPI_PERIPHERAL_CLKSRC {IO PLL} \
571. CONFIG.PCW_QSPI_PERIPHERAL_DIVISOR0 {5} \
572. CONFIG.PCW_QSPI_PERIPHERAL_ENABLE {1} \
573. CONFIG.PCW_QSPI_PERIPHERAL_FREQMHZ {200} \
574. CONFIG.PCW_QSPI_QSPI_IO {MIO 1 .. 6} \
575. CONFIG.PCW_SD0_GRP_CD_ENABLE {0} \
576. CONFIG.PCW_SD0_GRP_CD_IO {<Select>} \
577. CONFIG.PCW_SD0_GRP_POW_ENABLE {0} \
578. CONFIG.PCW_SD0_GRP_WP_ENABLE {0} \
579. CONFIG.PCW_SD0_PERIPHERAL_ENABLE {0} \
580. CONFIG.PCW_SD0_SD0_IO {<Select>} \
581. CONFIG.PCW_SDIO_PERIPHERAL_CLKSRC {IO PLL} \
582. CONFIG.PCW_SDIO_PERIPHERAL_DIVISOR0 {1} \
583. CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ {50} \
584. CONFIG.PCW_SDIO_PERIPHERAL_VALID {0} \
585. CONFIG.PCW_SINGLE_QSPI_DATA_MODE {x4} \
586. CONFIG.PCW_SMC_PERIPHERAL_CLKSRC {IO PLL} \
587. CONFIG.PCW_SMC_PERIPHERAL_DIVISOR0 {1} \
588. CONFIG.PCW_SMC_PERIPHERAL_FREQMHZ {100} \
589. CONFIG.PCW_SPI_PERIPHERAL_DIVISOR0 {1} \
590. CONFIG.PCW_TPIU_PERIPHERAL_CLKSRC {External} \
591. CONFIG.PCW_TPIU_PERIPHERAL_DIVISOR0 {1} \
592. CONFIG.PCW_TPIU_PERIPHERAL_FREQMHZ {200} \
593. CONFIG.PCW_UART1_BAUD_RATE {115200} \
594. CONFIG.PCW_UART1_GRP_FULL_ENABLE {0} \
595. CONFIG.PCW_UART1_PERIPHERAL_ENABLE {1} \
596. CONFIG.PCW_UART1_UART1_IO {MIO 48 .. 49} \
597. CONFIG.PCW_UART_PERIPHERAL_CLKSRC {IO PLL} \
598. CONFIG.PCW_UART_PERIPHERAL_DIVISOR0 {10} \
599. CONFIG.PCW_UART_PERIPHERAL_FREQMHZ {100} \
600. CONFIG.PCW_UART_PERIPHERAL_VALID {1} \
601. CONFIG.PCW_UIPARAM_ACT_DDR_FREQ_MHZ {533.333374} \
602. CONFIG.PCW_UIPARAM_DDR_ADV_ENABLE {0} \
603. CONFIG.PCW_UIPARAM_DDR_AL {0} \
604. CONFIG.PCW_UIPARAM_DDR_BANK_ADDR_COUNT {3} \
605. CONFIG.PCW_UIPARAM_DDR_BL {8} \
606. CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0 {0.221} \
607. CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1 {0.222} \
608. CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2 {0.217} \
609. CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3 {0.244} \
610. CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH {32 Bit} \
611. CONFIG.PCW_UIPARAM_DDR_CL {7} \
612. CONFIG.PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM {18.8} \
613. CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH {80.4535} \
614. CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY {160} \
615. CONFIG.PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM {18.8} \
616. CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH {80.4535} \
617. CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY {160} \
618. CONFIG.PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM {18.8} \
619. CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH {80.4535} \
620. CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY {160} \
621. CONFIG.PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM {18.8} \
622. CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH {80.4535} \
623. CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY {160} \
624. CONFIG.PCW_UIPARAM_DDR_CLOCK_STOP_EN {0} \
625. CONFIG.PCW_UIPARAM_DDR_COL_ADDR_COUNT {10} \
626. CONFIG.PCW_UIPARAM_DDR_CWL {6} \
627. CONFIG.PCW_UIPARAM_DDR_DEVICE_CAPACITY {4096 MBits} \
628. CONFIG.PCW_UIPARAM_DDR_DQS_0_LENGTH_MM {22.8} \
629. CONFIG.PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH {105.056} \
630. CONFIG.PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY {160} \
631. CONFIG.PCW_UIPARAM_DDR_DQS_1_LENGTH_MM {27.9} \
632. CONFIG.PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH {66.904} \
633. CONFIG.PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY {160} \
634. CONFIG.PCW_UIPARAM_DDR_DQS_2_LENGTH_MM {22.9} \
635. CONFIG.PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH {89.1715} \
636. CONFIG.PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY {160} \
637. CONFIG.PCW_UIPARAM_DDR_DQS_3_LENGTH_MM {29.4} \
638. CONFIG.PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH {113.63} \
639. CONFIG.PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY {160} \
640. CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 {-0.050} \
641. CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 {-0.044} \
642. CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 {-0.035} \
643. CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 {-0.100} \
644. CONFIG.PCW_UIPARAM_DDR_DQ_0_LENGTH_MM {22.8} \
645. CONFIG.PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH {98.503} \
646. CONFIG.PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY {160} \
647. CONFIG.PCW_UIPARAM_DDR_DQ_1_LENGTH_MM {27.9} \
648. CONFIG.PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH {68.5855} \
649. CONFIG.PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY {160} \
650. CONFIG.PCW_UIPARAM_DDR_DQ_2_LENGTH_MM {22.9} \
651. CONFIG.PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH {90.295} \
652. CONFIG.PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY {160} \
653. CONFIG.PCW_UIPARAM_DDR_DQ_3_LENGTH_MM {29.4} \
654. CONFIG.PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH {103.977} \
655. CONFIG.PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY {160} \
656. CONFIG.PCW_UIPARAM_DDR_DRAM_WIDTH {16 Bits} \
657. CONFIG.PCW_UIPARAM_DDR_ECC {Disabled} \
658. CONFIG.PCW_UIPARAM_DDR_ENABLE {1} \
659. CONFIG.PCW_UIPARAM_DDR_FREQ_MHZ {533.333333} \
660. CONFIG.PCW_UIPARAM_DDR_HIGH_TEMP {Normal (0-85)} \
661. CONFIG.PCW_UIPARAM_DDR_MEMORY_TYPE {DDR 3 (Low Voltage)} \
662. CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41K256M16 RE-125} \
663. CONFIG.PCW_UIPARAM_DDR_ROW_ADDR_COUNT {15} \
664. CONFIG.PCW_UIPARAM_DDR_SPEED_BIN {DDR3_1066F} \
665. CONFIG.PCW_UIPARAM_DDR_TRAIN_DATA_EYE {1} \
666. CONFIG.PCW_UIPARAM_DDR_TRAIN_READ_GATE {1} \
667. CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL {1} \
668. CONFIG.PCW_UIPARAM_DDR_T_FAW {40.0} \
669. CONFIG.PCW_UIPARAM_DDR_T_RAS_MIN {35.0} \
670. CONFIG.PCW_UIPARAM_DDR_T_RC {48.75} \
671. CONFIG.PCW_UIPARAM_DDR_T_RCD {7} \
672. CONFIG.PCW_UIPARAM_DDR_T_RP {7} \
673. CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF {0} \
674. CONFIG.PCW_USB0_PERIPHERAL_ENABLE {0} \
675. CONFIG.PCW_USB0_PERIPHERAL_FREQMHZ {60} \
676. CONFIG.PCW_USB0_RESET_ENABLE {1} \
677. CONFIG.PCW_USB0_RESET_IO {MIO 46} \
678. CONFIG.PCW_USB0_USB0_IO {<Select>} \
679. CONFIG.PCW_USB1_RESET_ENABLE {0} \
680. CONFIG.PCW_USB_RESET_ENABLE {1} \
681. CONFIG.PCW_USB_RESET_POLARITY {Active Low} \
682. CONFIG.PCW_USB_RESET_SELECT {<Select>} \
683. CONFIG.PCW_USE_AXI_NONSECURE {0} \
684. CONFIG.PCW_USE_CROSS_TRIGGER {0} \
685. CONFIG.PCW_USE_M_AXI_GP0 {0} \
686. ] $processing_system7_0
688. # Create interface connections
689. connect_bd_intf_net -intf_net processing_system7_0_DDR [get_bd_intf_ports DDR] [get_bd_intf_pins processing_system7_0/DDR]
690. connect_bd_intf_net -intf_net processing_system7_0_FIXED_IO [get_bd_intf_ports FIXED_IO] [get_bd_intf_pins processing_system7_0/FIXED_IO]
691. connect_bd_intf_net -intf_net processing_system7_0_GPIO_0 [get_bd_intf_ports GPIO_0_0] [get_bd_intf_pins processing_system7_0/GPIO_0]
693. # Create port connections
695. # Create address segments
697. # Perform GUI Layout
698. regenerate_bd_layout -layout_string {
699. "ActiveEmotionalView":"Default View",
700. "Default View_ScaleFactor":"1.0",
701. "Default View_TopLeft":"-337,-352",
702. "ExpandedHierarchyInLayout":"",
703. "guistr":"# # String gsaved with Nlview 7.0r6 2020-01-29 bk=1.5227 VDI=41 GEI=36 GUI=JA:10.0 non-TLS
704. # -string -flagsOSRD
705. preplace port DDR -pg 1 -lvl 2 -x 430 -y -120 -defaultsOSRD
706. preplace port FIXED_IO -pg 1 -lvl 2 -x 430 -y -100 -defaultsOSRD
707. preplace port GPIO_0_0 -pg 1 -lvl 2 -x 430 -y -140 -defaultsOSRD
708. preplace inst processing_system7_0 -pg 1 -lvl 1 -x 210 -y -100 -defaultsOSRD
709. preplace netloc processing_system7_0_GPIO_0 1 1 1 N -140
710. preplace netloc processing_system7_0_FIXED_IO 1 1 1 NJ -100
711. preplace netloc processing_system7_0_DDR 1 1 1 NJ -120
712. levelinfo -pg 1 0 210 430
713. pagesize -pg 1 -db -bbox -sgen 0 -220 550 200
714. "
715. }
717. # Restore current instance
718. current_bd_instance $oldCurInst
720. validate_bd_design
721. save_bd_design
722. close_bd_design $design_name
723. }
724. cr_bd_design_1 ""
     INFO: [BD::TCL 103-2010] Currently there is no design <design_1> in project, so creating one...
     Wrote : <C:\AimaginProjects\Zybo\Hardware_Z7000\i2c_demo\project_1\project_1.srcs\sources_1\bd\design_1\design_1.bd>
     create_bd_design: Time (s): cpu = 00:00:04 ; elapsed = 00:00:07 . Memory (MB): peak = 1119.531 ; gain = 0.000
     INFO: [BD::TCL 103-2011] Checking if the following IPs exist in the project's IP catalog:
     xilinx.com:ip:processing_system7:5.5 .
     CRITICAL WARNING: [PSU-1] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.050 . PS DDR interfaces might fail when entering negative DQS skew values.
     CRITICAL WARNING: [PSU-2] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.044 . PS DDR interfaces might fail when entering negative DQS skew values.
     CRITICAL WARNING: [PSU-3] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 has negative value -0.035 . PS DDR interfaces might fail when entering negative DQS skew values.
     CRITICAL WARNING: [PSU-4] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 has negative value -0.100 . PS DDR interfaces might fail when entering negative DQS skew values.
     CRITICAL WARNING: [PSU-1] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.050 . PS DDR interfaces might fail when entering negative DQS skew values.
     CRITICAL WARNING: [PSU-2] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.044 . PS DDR interfaces might fail when entering negative DQS skew values.
     CRITICAL WARNING: [PSU-3] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 has negative value -0.035 . PS DDR interfaces might fail when entering negative DQS skew values.
     CRITICAL WARNING: [PSU-4] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 has negative value -0.100 . PS DDR interfaces might fail when entering negative DQS skew values.
     Wrote : <C:\AimaginProjects\Zybo\Hardware_Z7000\i2c_demo\project_1\project_1.srcs\sources_1\bd\design_1\design_1.bd>
     Wrote : <C:/AimaginProjects/Zybo/Hardware_Z7000/i2c_demo/project_1/project_1.srcs/sources_1/bd/design_1/ui/bd_1f5defd0.ui>
725. set_property REGISTERED_WITH_MANAGER "1" [get_files design_1.bd ]
726. set_property SYNTH_CHECKPOINT_MODE "Hierarchical" [get_files design_1.bd ]
727. if { [get_property IS_LOCKED [ get_files -norecurse design_1.bd] ] == 1 } {
728. import_files -fileset sources_1 [file normalize "${origin_dir}/project_1/project_1.gen/sources_1/bd/design_1/hdl/design_1_wrapper.vhd" ]
729. } else {
730. set wrapper_path [make_wrapper -fileset sources_1 -files [ get_files -norecurse design_1.bd] -top]
731. add_files -norecurse -fileset sources_1 $wrapper_path
732. }
     INFO: [BD 41-1662] The design 'design_1.bd' is already validated. Therefore parameter propagation will not be re-run.
     VHDL Output written to : c:/AimaginProjects/Zybo/Hardware_Z7000/i2c_demo/project_1/project_1.gen/sources_1/bd/design_1/synth/design_1.vhd
     VHDL Output written to : c:/AimaginProjects/Zybo/Hardware_Z7000/i2c_demo/project_1/project_1.gen/sources_1/bd/design_1/sim/design_1.vhd
     VHDL Output written to : c:/AimaginProjects/Zybo/Hardware_Z7000/i2c_demo/project_1/project_1.gen/sources_1/bd/design_1/hdl/design_1_wrapper.vhd
     make_wrapper: Time (s): cpu = 00:00:01 ; elapsed = 00:00:07 . Memory (MB): peak = 1420.555 ; gain = 126.723
733. if {[string equal [get_runs -quiet synth_1] ""]} {
734. create_run -name synth_1 -part xc7z020clg400-1 -flow {Vivado Synthesis 2020} -strategy "Vivado Synthesis Defaults" -report_strategy {No Reports} -constrset constrs_1
735. } else {
736. set_property strategy "Vivado Synthesis Defaults" [get_runs synth_1]
737. set_property flow "Vivado Synthesis 2020" [get_runs synth_1]
738. }
739. set obj [get_runs synth_1]
740. set_property set_report_strategy_name 1 $obj
741. set_property report_strategy {Vivado Synthesis Default Reports} $obj
742. set_property set_report_strategy_name 0 $obj
743. if { [ string equal [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0] "" ] } {
744. create_report_config -report_name synth_1_synth_report_utilization_0 -report_type report_utilization:1.0 -steps synth_design -runs synth_1
745. }
746. set obj [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0]
747. if { $obj != "" } {
749. }
750. set obj [get_runs synth_1]
751. set_property -name "strategy" -value "Vivado Synthesis Defaults" -objects $obj
752. current_run -synthesis [get_runs synth_1]
753. if {[string equal [get_runs -quiet impl_1] ""]} {
754. create_run -name impl_1 -part xc7z020clg400-1 -flow {Vivado Implementation 2020} -strategy "Vivado Implementation Defaults" -report_strategy {No Reports} -constrset constrs_1 -parent_run synth_1
755. } else {
756. set_property strategy "Vivado Implementation Defaults" [get_runs impl_1]
757. set_property flow "Vivado Implementation 2020" [get_runs impl_1]
758. }
759. set obj [get_runs impl_1]
760. set_property set_report_strategy_name 1 $obj
761. set_property report_strategy {Vivado Implementation Default Reports} $obj
762. set_property set_report_strategy_name 0 $obj
763. if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0] "" ] } {
764. create_report_config -report_name impl_1_init_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps init_design -runs impl_1
765. }
766. set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0]
767. if { $obj != "" } {
768. set_property -name "is_enabled" -value "0" -objects $obj
769. set_property -name "options.max_paths" -value "10" -objects $obj
771. }
772. if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0] "" ] } {
773. create_report_config -report_name impl_1_opt_report_drc_0 -report_type report_drc:1.0 -steps opt_design -runs impl_1
774. }
775. set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0]
776. if { $obj != "" } {
778. }
779. if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0] "" ] } {
780. create_report_config -report_name impl_1_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps opt_design -runs impl_1
781. }
782. set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0]
783. if { $obj != "" } {
784. set_property -name "is_enabled" -value "0" -objects $obj
785. set_property -name "options.max_paths" -value "10" -objects $obj
787. }
788. if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0] "" ] } {
789. create_report_config -report_name impl_1_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps power_opt_design -runs impl_1
790. }
791. set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0]
792. if { $obj != "" } {
793. set_property -name "is_enabled" -value "0" -objects $obj
794. set_property -name "options.max_paths" -value "10" -objects $obj
796. }
797. if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0] "" ] } {
798. create_report_config -report_name impl_1_place_report_io_0 -report_type report_io:1.0 -steps place_design -runs impl_1
799. }
800. set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0]
801. if { $obj != "" } {
803. }
804. if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0] "" ] } {
805. create_report_config -report_name impl_1_place_report_utilization_0 -report_type report_utilization:1.0 -steps place_design -runs impl_1
806. }
807. set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0]
808. if { $obj != "" } {
810. }
811. if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0] "" ] } {
812. create_report_config -report_name impl_1_place_report_control_sets_0 -report_type report_control_sets:1.0 -steps place_design -runs impl_1
813. }
814. set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0]
815. if { $obj != "" } {
816. set_property -name "options.verbose" -value "1" -objects $obj
818. }
819. if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0] "" ] } {
820. create_report_config -report_name impl_1_place_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1
821. }
822. set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0]
823. if { $obj != "" } {
824. set_property -name "is_enabled" -value "0" -objects $obj
826. }
827. if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1] "" ] } {
828. create_report_config -report_name impl_1_place_report_incremental_reuse_1 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1
829. }
830. set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1]
831. if { $obj != "" } {
832. set_property -name "is_enabled" -value "0" -objects $obj
834. }
835. if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0] "" ] } {
836. create_report_config -report_name impl_1_place_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps place_design -runs impl_1
837. }
838. set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0]
839. if { $obj != "" } {
840. set_property -name "is_enabled" -value "0" -objects $obj
841. set_property -name "options.max_paths" -value "10" -objects $obj
843. }
844. if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0] "" ] } {
845. create_report_config -report_name impl_1_post_place_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_place_power_opt_design -runs impl_1
846. }
847. set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0]
848. if { $obj != "" } {
849. set_property -name "is_enabled" -value "0" -objects $obj
850. set_property -name "options.max_paths" -value "10" -objects $obj
852. }
853. if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0] "" ] } {
854. create_report_config -report_name impl_1_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps phys_opt_design -runs impl_1
855. }
856. set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0]
857. if { $obj != "" } {
858. set_property -name "is_enabled" -value "0" -objects $obj
859. set_property -name "options.max_paths" -value "10" -objects $obj
861. }
862. if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0] "" ] } {
863. create_report_config -report_name impl_1_route_report_drc_0 -report_type report_drc:1.0 -steps route_design -runs impl_1
864. }
865. set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0]
866. if { $obj != "" } {
868. }
869. if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0] "" ] } {
870. create_report_config -report_name impl_1_route_report_methodology_0 -report_type report_methodology:1.0 -steps route_design -runs impl_1
871. }
872. set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0]
873. if { $obj != "" } {
875. }
876. if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0] "" ] } {
877. create_report_config -report_name impl_1_route_report_power_0 -report_type report_power:1.0 -steps route_design -runs impl_1
878. }
879. set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0]
880. if { $obj != "" } {
882. }
883. if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0] "" ] } {
884. create_report_config -report_name impl_1_route_report_route_status_0 -report_type report_route_status:1.0 -steps route_design -runs impl_1
885. }
886. set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0]
887. if { $obj != "" } {
889. }
890. if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0] "" ] } {
891. create_report_config -report_name impl_1_route_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps route_design -runs impl_1
892. }
893. set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0]
894. if { $obj != "" } {
895. set_property -name "options.max_paths" -value "10" -objects $obj
897. }
898. if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0] "" ] } {
899. create_report_config -report_name impl_1_route_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps route_design -runs impl_1
900. }
901. set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0]
902. if { $obj != "" } {
904. }
905. if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0] "" ] } {
906. create_report_config -report_name impl_1_route_report_clock_utilization_0 -report_type report_clock_utilization:1.0 -steps route_design -runs impl_1
907. }
908. set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0]
909. if { $obj != "" } {
911. }
912. if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0] "" ] } {
913. create_report_config -report_name impl_1_route_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps route_design -runs impl_1
914. }
915. set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0]
916. if { $obj != "" } {
917. set_property -name "options.warn_on_violation" -value "1" -objects $obj
919. }
920. if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0] "" ] } {
921. create_report_config -report_name impl_1_post_route_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_route_phys_opt_design -runs impl_1
922. }
923. set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0]
924. if { $obj != "" } {
925. set_property -name "options.max_paths" -value "10" -objects $obj
926. set_property -name "options.warn_on_violation" -value "1" -objects $obj
928. }
929. if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0] "" ] } {
930. create_report_config -report_name impl_1_post_route_phys_opt_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps post_route_phys_opt_design -runs impl_1
931. }
932. set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0]
933. if { $obj != "" } {
934. set_property -name "options.warn_on_violation" -value "1" -objects $obj
936. }
937. set obj [get_runs impl_1]
938. set_property -name "strategy" -value "Vivado Implementation Defaults" -objects $obj
939. set_property -name "steps.write_bitstream.args.readback_file" -value "0" -objects $obj
940. set_property -name "steps.write_bitstream.args.verbose" -value "0" -objects $obj
941. current_run -implementation [get_runs impl_1]
942. puts "INFO: Project created:${_xil_proj_name_}"
     INFO: Project created:project_1
943. if {[string equal [get_dashboard_gadgets [ list "drc_1" ] ] ""]} {
944. create_dashboard_gadget -name {drc_1} -type drc
945. }
946. set obj [get_dashboard_gadgets [ list "drc_1" ] ]
947. set_property -name "reports" -value "impl_1#impl_1_route_report_drc_0" -objects $obj
948. if {[string equal [get_dashboard_gadgets [ list "methodology_1" ] ] ""]} {
949. create_dashboard_gadget -name {methodology_1} -type methodology
950. }
951. set obj [get_dashboard_gadgets [ list "methodology_1" ] ]
952. set_property -name "reports" -value "impl_1#impl_1_route_report_methodology_0" -objects $obj
953. if {[string equal [get_dashboard_gadgets [ list "power_1" ] ] ""]} {
954. create_dashboard_gadget -name {power_1} -type power
955. }
956. set obj [get_dashboard_gadgets [ list "power_1" ] ]
957. set_property -name "reports" -value "impl_1#impl_1_route_report_power_0" -objects $obj
958. if {[string equal [get_dashboard_gadgets [ list "timing_1" ] ] ""]} {
959. create_dashboard_gadget -name {timing_1} -type timing
960. }
961. set obj [get_dashboard_gadgets [ list "timing_1" ] ]
962. set_property -name "reports" -value "impl_1#impl_1_route_report_timing_summary_0" -objects $obj
963. if {[string equal [get_dashboard_gadgets [ list "utilization_1" ] ] ""]} {
964. create_dashboard_gadget -name {utilization_1} -type utilization
965. }
966. set obj [get_dashboard_gadgets [ list "utilization_1" ] ]
967. set_property -name "reports" -value "synth_1#synth_1_synth_report_utilization_0" -objects $obj
968. set_property -name "run.step" -value "synth_design" -objects $obj
969. set_property -name "run.type" -value "synthesis" -objects $obj
970. if {[string equal [get_dashboard_gadgets [ list "utilization_2" ] ] ""]} {
971. create_dashboard_gadget -name {utilization_2} -type utilization
972. }
973. set obj [get_dashboard_gadgets [ list "utilization_2" ] ]
974. set_property -name "reports" -value "impl_1#impl_1_place_report_utilization_0" -objects $obj
975. move_dashboard_gadget -name {utilization_1} -row 0 -col 0
976. move_dashboard_gadget -name {power_1} -row 1 -col 0
977. move_dashboard_gadget -name {drc_1} -row 2 -col 0
978. move_dashboard_gadget -name {timing_1} -row 0 -col 1
979. move_dashboard_gadget -name {utilization_2} -row 1 -col 1
980. move_dashboard_gadget -name {methodology_1} -row 2 -col 1
     update_compile_order -fileset sources_1

Hi Johan,

Thank you for the valuable feedback.
The root cause of this issue is absolute path definitions instead of relative file path definitions inside the tcl file.
Please replace your tcl file located at ".../demo/i2c_demo/hardware_design/vivado_tcl" folder with the attached file and update us with your findings.

Hello Shawn,

Thanks for the updated .tcl file, this one works fine.
Besides the 8 critical warnings (which do not harm according to the link you've sent me) there is another warning: [IP_Flow 19-474] Invalid Parameter 'Component_Name'. It would be nice to solve that as wel in the future.
Another remark: the created project is called project_1. In case of other hardware projects (for example the adc_demo) the project is called adc_demo (which I like). In case of the gpio_demo the project is called zynq7000_gpio_demo. I prefer gpio_demo to be consistent.
Last remark (for this issue:-) ): It would be very nice if there was only one hardware configuration (.tcl / .xdc) that works for all demo's (I put that whish in the suggestions forum some time ago). That makes maintenance of the hardware much easier. And also combining partial models form the various demo's.

Regards!
johan.

Differences between original and new .tcl file:

Hi Johan,

Thank you for the feedback.
1. Regarding warning: [IP_Flow 19-474] Invalid Parameter 'Component_Name'., we are unable to recreate this error from our end. Would it be possible to attach the full log so we can have an understanding at which point the warning is being thrown?
2. We will try to implement a consistent naming scheme for the projects created via tcl files in our future releases.
3. We are aware of the need and appeal of a hardware reference file that works with all of the demos. We will update you further on this matter on the feature request when we have come to a decision.

Best Regards,
Shawn

Hello Shawn,

Interestingly I did not get the warning after rebuilding the hardware myself. It has solved itself somehow :-)
Below my logfile and the status messages.
Regards,
johan.
.

source i2c_demo.tcl

1. proc checkRequiredFiles { origin_dir} {
2. set status true
3. set files [list \
4. "xdc/My_Zybo-Z7-Master.xdc" \
5. ]
6. foreach ifile $files {
7. if { ![file isfile $ifile] } {
8. puts " Could not find remote file $ifile "
9. set status false
10. }
11. }
13. return $status
14. }
15. set origin_dir "."
16. if { [info exists ::origin_dir_loc] } {
17. set origin_dir $::origin_dir_loc
18. }
19. set xil_proj_name "project_1"
20. if { [info exists ::user_project_name] } {
21. set xil_proj_name $::user_project_name
22. }
23. variable script_file
24. set script_file "i2c_demo.tcl"
25. proc print_help {} {
26. variable script_file
27. puts "\nDescription:"
28. puts "Recreate a Vivado project from this script. The created project will be"
29. puts "functionally equivalent to the original project for which this script was"
30. puts "generated. The script contains commands for creating a project, filesets,"
31. puts "runs, adding/importing sources and setting properties on various objects.\n"
32. puts "Syntax:"
33. puts "$script_file"
34. puts "$script_file -tclargs \[--origin_dir <path>\]"
35. puts "$script_file -tclargs \[--project_name <name>\]"
36. puts "$script_file -tclargs \[--help\]\n"
37. puts "Usage:"
38. puts "Name Description"
39. puts "-------------------------------------------------------------------------"
40. puts "\[--origin_dir <path>\] Determine source file paths wrt this path. Default"
41. puts " origin_dir path value is \".\", otherwise, the value"
42. puts " that was set with the \"-paths_relative_to\" switch"
43. puts " when this script was generated.\n"
44. puts "\[--project_name <name>\] Create project with the specified name. Default"
45. puts " name is the name of the project from where this"
46. puts " script was generated.\n"
47. puts "\[--help\] Print help information for this script"
48. puts "-------------------------------------------------------------------------\n"
49. exit 0
50. }
51. if { $::argc > 0 } {
52. for {set i 0} {$i < $::argc} {incr i} {
53. set option [string trim [lindex $::argv $i]]
54. switch regexp - $option {
55. "--origin_dir" { incr i; set origin_dir [lindex $::argv $i] }
56. "--project_name" { incr i; set xil_proj_name [lindex $::argv $i] }
57. "--help" { print_help }
58. default {
59. if { [regexp {^-} $option] } {
60. puts "ERROR: Unknown option '$option' specified, please type '$script_file -tclargs --help' for usage info.\n"
61. return 1
62. }
63. }
64. }
65. }
66. }
67. set orig_proj_dir "[file normalize "$origin_dir/project_1"]"
68. set validate_required 0
69. if { $validate_required } {
70. if { [checkRequiredFiles $origin_dir] } {
71. puts "Tcl file $script_file is valid. All files required for project creation is accesable. "
72. } else {
73. puts "Tcl file $script_file is not valid. Not all files required for project creation is accesable. "
74. return
75. }
76. }
77. create_project ${_xil_proj_name_} ./${_xil_proj_name_} -part xc7z020clg400-1
    INFO: [IP_Flow 19-234] Refreshing IP repositories
    INFO: [IP_Flow 19-1704] No user IP repositories specified
    INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2020.2/data/ip'.
    create_project: Time (s): cpu = 00:00:04 ; elapsed = 00:00:07 . Memory (MB): peak = 1115.910 ; gain = 0.000
78. set proj_dir [get_property directory [current_project]]
79. set obj [current_project]
80. set_property -name "board_part" -value "digilentinc.com:zybo-z7-20:part0:1.0" -objects $obj
81. set_property -name "default_lib" -value "xil_defaultlib" -objects $obj
82. set_property -name "enable_vhdl_2008" -value "1" -objects $obj
83. set_property -name "ip_cache_permissions" -value "read write" -objects $obj
84. set_property -name "ip_output_repo" -value "$proj_dir/${_xil_proj_name_}.cache/ip" -objects $obj
85. set_property -name "mem.enable_memory_map_generation" -value "1" -objects $obj
86. set_property -name "platform.board_id" -value "zybo-z7-20" -objects $obj
87. set_property -name "sim.central_dir" -value "$proj_dir/${_xil_proj_name_}.ip_user_files" -objects $obj
88. set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj
89. set_property -name "simulator_language" -value "Mixed" -objects $obj
90. set_property -name "target_language" -value "VHDL" -objects $obj
91. if {[string equal [get_filesets -quiet sources_1] ""]} {
92. create_fileset -srcset sources_1
93. }
94. set obj [get_filesets sources_1]
95. set obj [get_filesets sources_1]
96. set_property -name "top" -value "design_1_wrapper" -objects $obj
97. if {[string equal [get_filesets -quiet constrs_1] ""]} {
98. create_fileset -constrset constrs_1
99. }
100. set obj [get_filesets constrs_1]
101. set file "[file normalize "xdc/My_Zybo-Z7-Master.xdc"]"
102. set file_added [add_files -norecurse -fileset $obj [list $file]]
103. set file "xdc/My_Zybo-Z7-Master.xdc"
104. set file [file normalize $file]
105. set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]]
106. set_property -name "file_type" -value "XDC" -objects $file_obj
107. set obj [get_filesets constrs_1]
108. if {[string equal [get_filesets -quiet sim_1] ""]} {
109. create_fileset -simset sim_1
110. }
111. set obj [get_filesets sim_1]
112. set obj [get_filesets sim_1]
113. set_property -name "hbs.configure_design_for_hier_access" -value "1" -objects $obj
114. set_property -name "top" -value "design_1_wrapper" -objects $obj
115. set_property -name "top_lib" -value "xil_defaultlib" -objects $obj
116. set obj [get_filesets utils_1]
117. set obj [get_filesets utils_1]
118. proc cr_bd_design_1 { parentCell } {
120. # CHANGE DESIGN NAME HERE
121. set design_name design_1
123. common::send_gid_msg -ssname BD::TCL -id 2010 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..."
125. create_bd_design $design_name
127. set bCheckIPsPassed 1
128. ##################################################################
129. # CHECK IPs
130. ##################################################################
131. set bCheckIPs 1
132. if { $bCheckIPs == 1 } {
133. set list_check_ips "\
134. xilinx.com:ip:processing_system7:5.5\
135. "
137. set list_ips_missing ""
138. common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
140. foreach ip_vlnv $list_check_ips {
141. set ip_obj [get_ipdefs -all $ip_vlnv]
142. if { $ip_obj eq "" } {
143. lappend list_ips_missing $ip_vlnv
144. }
145. }
147. if { $list_ips_missing ne "" } {
148. catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP to the project." }
149. set bCheckIPsPassed 0
150. }
152. }
154. if { $bCheckIPsPassed != 1 } {
155. common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above."
156. return 3
157. }
159. variable script_folder
161. if { $parentCell eq "" } {
162. set parentCell [get_bd_cells /]
163. }
165. # Get object for parentCell
166. set parentObj [get_bd_cells $parentCell]
167. if { $parentObj == "" } {
168. catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
169. return
170. }
172. # Make sure parentObj is hier blk
173. set parentType [get_property TYPE $parentObj]
174. if { $parentType ne "hier" } {
175. catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
176. return
177. }
179. # Save current instance; Restore later
180. set oldCurInst [current_bd_instance .]
182. # Set parent object as current
183. current_bd_instance $parentObj
186. # Create interface ports
187. set DDR [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR ]
189. set FIXED_IO [ create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 FIXED_IO ]
191. set GPIO_0_0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 GPIO_0_0 ]
194. # Create ports
196. # Create instance: processing_system7_0, and set properties
197. set processing_system7_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0 ]
198. set_property -dict [ list \
199. CONFIG.PCW_ACT_APU_PERIPHERAL_FREQMHZ {666.666687} \
200. CONFIG.PCW_ACT_CAN_PERIPHERAL_FREQMHZ {10.000000} \
201. CONFIG.PCW_ACT_DCI_PERIPHERAL_FREQMHZ {10.158730} \
202. CONFIG.PCW_ACT_ENET0_PERIPHERAL_FREQMHZ {125.000000} \
203. CONFIG.PCW_ACT_ENET1_PERIPHERAL_FREQMHZ {10.000000} \
204. CONFIG.PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ {50.000000} \
205. CONFIG.PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ {10.000000} \
206. CONFIG.PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ {10.000000} \
207. CONFIG.PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ {10.000000} \
208. CONFIG.PCW_ACT_PCAP_PERIPHERAL_FREQMHZ {200.000000} \
209. CONFIG.PCW_ACT_QSPI_PERIPHERAL_FREQMHZ {200.000000} \
210. CONFIG.PCW_ACT_SDIO_PERIPHERAL_FREQMHZ {10.000000} \
211. CONFIG.PCW_ACT_SMC_PERIPHERAL_FREQMHZ {10.000000} \
212. CONFIG.PCW_ACT_SPI_PERIPHERAL_FREQMHZ {10.000000} \
213. CONFIG.PCW_ACT_TPIU_PERIPHERAL_FREQMHZ {200.000000} \
214. CONFIG.PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ {111.111115} \
215. CONFIG.PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ {111.111115} \
216. CONFIG.PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ {111.111115} \
217. CONFIG.PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ {111.111115} \
218. CONFIG.PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ {111.111115} \
219. CONFIG.PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ {111.111115} \
220. CONFIG.PCW_ACT_UART_PERIPHERAL_FREQMHZ {100.000000} \
221. CONFIG.PCW_ACT_WDT_PERIPHERAL_FREQMHZ {111.111115} \
222. CONFIG.PCW_APU_CLK_RATIO_ENABLE {6:2:1} \
223. CONFIG.PCW_APU_PERIPHERAL_FREQMHZ {667} \
224. CONFIG.PCW_ARMPLL_CTRL_FBDIV {40} \
225. CONFIG.PCW_CAN_PERIPHERAL_DIVISOR0 {1} \
226. CONFIG.PCW_CAN_PERIPHERAL_DIVISOR1 {1} \
227. CONFIG.PCW_CLK0_FREQ {50000000} \
228. CONFIG.PCW_CLK1_FREQ {10000000} \
229. CONFIG.PCW_CLK2_FREQ {10000000} \
230. CONFIG.PCW_CLK3_FREQ {10000000} \
231. CONFIG.PCW_CPU_CPU_6X4X_MAX_RANGE {667} \
232. CONFIG.PCW_CPU_CPU_PLL_FREQMHZ {1333.333} \
233. CONFIG.PCW_CPU_PERIPHERAL_CLKSRC {ARM PLL} \
234. CONFIG.PCW_CPU_PERIPHERAL_DIVISOR0 {2} \
235. CONFIG.PCW_CRYSTAL_PERIPHERAL_FREQMHZ {33.333333} \
236. CONFIG.PCW_DCI_PERIPHERAL_CLKSRC {DDR PLL} \
237. CONFIG.PCW_DCI_PERIPHERAL_DIVISOR0 {15} \
238. CONFIG.PCW_DCI_PERIPHERAL_DIVISOR1 {7} \
239. CONFIG.PCW_DCI_PERIPHERAL_FREQMHZ {10.159} \
240. CONFIG.PCW_DDRPLL_CTRL_FBDIV {32} \
241. CONFIG.PCW_DDR_DDR_PLL_FREQMHZ {1066.667} \
242. CONFIG.PCW_DDR_HPRLPR_QUEUE_PARTITION {HPR/LPR} \
243. CONFIG.PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL {15} \
244. CONFIG.PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL {2} \
245. CONFIG.PCW_DDR_PERIPHERAL_CLKSRC {DDR PLL} \
246. CONFIG.PCW_DDR_PERIPHERAL_DIVISOR0 {2} \
247. CONFIG.PCW_DDR_PORT0_HPR_ENABLE {0} \
248. CONFIG.PCW_DDR_PORT1_HPR_ENABLE {0} \
249. CONFIG.PCW_DDR_PORT2_HPR_ENABLE {0} \
250. CONFIG.PCW_DDR_PORT3_HPR_ENABLE {0} \
251. CONFIG.PCW_DDR_RAM_HIGHADDR {0x3FFFFFFF} \
252. CONFIG.PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL {2} \
253. CONFIG.PCW_ENET0_ENET0_IO {MIO 16 .. 27} \
254. CONFIG.PCW_ENET0_GRP_MDIO_ENABLE {1} \
255. CONFIG.PCW_ENET0_GRP_MDIO_IO {MIO 52 .. 53} \
256. CONFIG.PCW_ENET0_PERIPHERAL_CLKSRC {IO PLL} \
257. CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR0 {8} \
258. CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR1 {1} \
259. CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {1} \
260. CONFIG.PCW_ENET0_PERIPHERAL_FREQMHZ {1000 Mbps} \
261. CONFIG.PCW_ENET0_RESET_ENABLE {0} \
262. CONFIG.PCW_ENET1_GRP_MDIO_ENABLE {0} \
263. CONFIG.PCW_ENET1_PERIPHERAL_CLKSRC {IO PLL} \
264. CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR0 {1} \
265. CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR1 {1} \
266. CONFIG.PCW_ENET1_PERIPHERAL_ENABLE {0} \
267. CONFIG.PCW_ENET1_PERIPHERAL_FREQMHZ {1000 Mbps} \
268. CONFIG.PCW_ENET1_RESET_ENABLE {0} \
269. CONFIG.PCW_ENET_RESET_ENABLE {1} \
270. CONFIG.PCW_ENET_RESET_POLARITY {Active Low} \
271. CONFIG.PCW_ENET_RESET_SELECT {Share reset pin} \
272. CONFIG.PCW_EN_4K_TIMER {0} \
273. CONFIG.PCW_EN_EMIO_ENET0 {0} \
274. CONFIG.PCW_EN_EMIO_GPIO {1} \
275. CONFIG.PCW_EN_EMIO_I2C0 {0} \
276. CONFIG.PCW_EN_EMIO_I2C1 {0} \
277. CONFIG.PCW_EN_ENET0 {1} \
278. CONFIG.PCW_EN_GPIO {1} \
279. CONFIG.PCW_EN_I2C0 {1} \
280. CONFIG.PCW_EN_I2C1 {1} \
281. CONFIG.PCW_EN_QSPI {1} \
282. CONFIG.PCW_EN_SDIO0 {0} \
283. CONFIG.PCW_EN_UART1 {1} \
284. CONFIG.PCW_EN_USB0 {0} \
285. CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR0 {5} \
286. CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR1 {4} \
287. CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR0 {1} \
288. CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR1 {1} \
289. CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR0 {1} \
290. CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR1 {1} \
291. CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR0 {1} \
292. CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR1 {1} \
293. CONFIG.PCW_FPGA_FCLK0_ENABLE {1} \
294. CONFIG.PCW_FPGA_FCLK1_ENABLE {0} \
295. CONFIG.PCW_FPGA_FCLK2_ENABLE {0} \
296. CONFIG.PCW_FPGA_FCLK3_ENABLE {0} \
297. CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {1} \
298. CONFIG.PCW_GPIO_EMIO_GPIO_IO {26} \
299. CONFIG.PCW_GPIO_EMIO_GPIO_WIDTH {26} \
300. CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1} \
301. CONFIG.PCW_GPIO_MIO_GPIO_IO {MIO} \
302. CONFIG.PCW_GPIO_PERIPHERAL_ENABLE {0} \
303. CONFIG.PCW_I2C0_GRP_INT_ENABLE {1} \
304. CONFIG.PCW_I2C0_GRP_INT_IO {EMIO} \
305. CONFIG.PCW_I2C0_I2C0_IO {MIO 14 .. 15} \
306. CONFIG.PCW_I2C0_PERIPHERAL_ENABLE {1} \
307. CONFIG.PCW_I2C0_RESET_ENABLE {0} \
308. CONFIG.PCW_I2C1_GRP_INT_ENABLE {1} \
309. CONFIG.PCW_I2C1_GRP_INT_IO {EMIO} \
310. CONFIG.PCW_I2C1_I2C1_IO {MIO 12 .. 13} \
311. CONFIG.PCW_I2C1_PERIPHERAL_ENABLE {1} \
312. CONFIG.PCW_I2C1_RESET_ENABLE {0} \
313. CONFIG.PCW_I2C_PERIPHERAL_FREQMHZ {111.111115} \
314. CONFIG.PCW_I2C_RESET_ENABLE {1} \
315. CONFIG.PCW_I2C_RESET_SELECT {Share reset pin} \
316. CONFIG.PCW_IOPLL_CTRL_FBDIV {30} \
317. CONFIG.PCW_IO_IO_PLL_FREQMHZ {1000.000} \
318. CONFIG.PCW_IRQ_F2P_MODE {DIRECT} \
319. CONFIG.PCW_MIO_0_DIRECTION {inout} \
320. CONFIG.PCW_MIO_0_IOTYPE {LVCMOS 3.3V} \
321. CONFIG.PCW_MIO_0_PULLUP {enabled} \
322. CONFIG.PCW_MIO_0_SLEW {slow} \
323. CONFIG.PCW_MIO_10_DIRECTION {inout} \
324. CONFIG.PCW_MIO_10_IOTYPE {LVCMOS 3.3V} \
325. CONFIG.PCW_MIO_10_PULLUP {enabled} \
326. CONFIG.PCW_MIO_10_SLEW {slow} \
327. CONFIG.PCW_MIO_11_DIRECTION {inout} \
328. CONFIG.PCW_MIO_11_IOTYPE {LVCMOS 3.3V} \
329. CONFIG.PCW_MIO_11_PULLUP {enabled} \
330. CONFIG.PCW_MIO_11_SLEW {slow} \
331. CONFIG.PCW_MIO_12_DIRECTION {inout} \
332. CONFIG.PCW_MIO_12_IOTYPE {LVCMOS 3.3V} \
333. CONFIG.PCW_MIO_12_PULLUP {enabled} \
334. CONFIG.PCW_MIO_12_SLEW {slow} \
335. CONFIG.PCW_MIO_13_DIRECTION {inout} \
336. CONFIG.PCW_MIO_13_IOTYPE {LVCMOS 3.3V} \
337. CONFIG.PCW_MIO_13_PULLUP {enabled} \
338. CONFIG.PCW_MIO_13_SLEW {slow} \
339. CONFIG.PCW_MIO_14_DIRECTION {inout} \
340. CONFIG.PCW_MIO_14_IOTYPE {LVCMOS 3.3V} \
341. CONFIG.PCW_MIO_14_PULLUP {enabled} \
342. CONFIG.PCW_MIO_14_SLEW {slow} \
343. CONFIG.PCW_MIO_15_DIRECTION {inout} \
344. CONFIG.PCW_MIO_15_IOTYPE {LVCMOS 3.3V} \
345. CONFIG.PCW_MIO_15_PULLUP {enabled} \
346. CONFIG.PCW_MIO_15_SLEW {slow} \
347. CONFIG.PCW_MIO_16_DIRECTION {out} \
348. CONFIG.PCW_MIO_16_IOTYPE {LVCMOS 1.8V} \
349. CONFIG.PCW_MIO_16_PULLUP {enabled} \
350. CONFIG.PCW_MIO_16_SLEW {fast} \
351. CONFIG.PCW_MIO_17_DIRECTION {out} \
352. CONFIG.PCW_MIO_17_IOTYPE {LVCMOS 1.8V} \
353. CONFIG.PCW_MIO_17_PULLUP {enabled} \
354. CONFIG.PCW_MIO_17_SLEW {fast} \
355. CONFIG.PCW_MIO_18_DIRECTION {out} \
356. CONFIG.PCW_MIO_18_IOTYPE {LVCMOS 1.8V} \
357. CONFIG.PCW_MIO_18_PULLUP {enabled} \
358. CONFIG.PCW_MIO_18_SLEW {fast} \
359. CONFIG.PCW_MIO_19_DIRECTION {out} \
360. CONFIG.PCW_MIO_19_IOTYPE {LVCMOS 1.8V} \
361. CONFIG.PCW_MIO_19_PULLUP {enabled} \
362. CONFIG.PCW_MIO_19_SLEW {fast} \
363. CONFIG.PCW_MIO_1_DIRECTION {out} \
364. CONFIG.PCW_MIO_1_IOTYPE {LVCMOS 3.3V} \
365. CONFIG.PCW_MIO_1_PULLUP {enabled} \
366. CONFIG.PCW_MIO_1_SLEW {slow} \
367. CONFIG.PCW_MIO_20_DIRECTION {out} \
368. CONFIG.PCW_MIO_20_IOTYPE {LVCMOS 1.8V} \
369. CONFIG.PCW_MIO_20_PULLUP {enabled} \
370. CONFIG.PCW_MIO_20_SLEW {fast} \
371. CONFIG.PCW_MIO_21_DIRECTION {out} \
372. CONFIG.PCW_MIO_21_IOTYPE {LVCMOS 1.8V} \
373. CONFIG.PCW_MIO_21_PULLUP {enabled} \
374. CONFIG.PCW_MIO_21_SLEW {fast} \
375. CONFIG.PCW_MIO_22_DIRECTION {in} \
376. CONFIG.PCW_MIO_22_IOTYPE {LVCMOS 1.8V} \
377. CONFIG.PCW_MIO_22_PULLUP {enabled} \
378. CONFIG.PCW_MIO_22_SLEW {fast} \
379. CONFIG.PCW_MIO_23_DIRECTION {in} \
380. CONFIG.PCW_MIO_23_IOTYPE {LVCMOS 1.8V} \
381. CONFIG.PCW_MIO_23_PULLUP {enabled} \
382. CONFIG.PCW_MIO_23_SLEW {fast} \
383. CONFIG.PCW_MIO_24_DIRECTION {in} \
384. CONFIG.PCW_MIO_24_IOTYPE {LVCMOS 1.8V} \
385. CONFIG.PCW_MIO_24_PULLUP {enabled} \
386. CONFIG.PCW_MIO_24_SLEW {fast} \
387. CONFIG.PCW_MIO_25_DIRECTION {in} \
388. CONFIG.PCW_MIO_25_IOTYPE {LVCMOS 1.8V} \
389. CONFIG.PCW_MIO_25_PULLUP {enabled} \
390. CONFIG.PCW_MIO_25_SLEW {fast} \
391. CONFIG.PCW_MIO_26_DIRECTION {in} \
392. CONFIG.PCW_MIO_26_IOTYPE {LVCMOS 1.8V} \
393. CONFIG.PCW_MIO_26_PULLUP {enabled} \
394. CONFIG.PCW_MIO_26_SLEW {fast} \
395. CONFIG.PCW_MIO_27_DIRECTION {in} \
396. CONFIG.PCW_MIO_27_IOTYPE {LVCMOS 1.8V} \
397. CONFIG.PCW_MIO_27_PULLUP {enabled} \
398. CONFIG.PCW_MIO_27_SLEW {fast} \
399. CONFIG.PCW_MIO_28_DIRECTION {inout} \
400. CONFIG.PCW_MIO_28_IOTYPE {LVCMOS 1.8V} \
401. CONFIG.PCW_MIO_28_PULLUP {enabled} \
402. CONFIG.PCW_MIO_28_SLEW {fast} \
403. CONFIG.PCW_MIO_29_DIRECTION {inout} \
404. CONFIG.PCW_MIO_29_IOTYPE {LVCMOS 1.8V} \
405. CONFIG.PCW_MIO_29_PULLUP {enabled} \
406. CONFIG.PCW_MIO_29_SLEW {fast} \
407. CONFIG.PCW_MIO_2_DIRECTION {inout} \
408. CONFIG.PCW_MIO_2_IOTYPE {LVCMOS 3.3V} \
409. CONFIG.PCW_MIO_2_PULLUP {disabled} \
410. CONFIG.PCW_MIO_2_SLEW {slow} \
411. CONFIG.PCW_MIO_30_DIRECTION {inout} \
412. CONFIG.PCW_MIO_30_IOTYPE {LVCMOS 1.8V} \
413. CONFIG.PCW_MIO_30_PULLUP {enabled} \
414. CONFIG.PCW_MIO_30_SLEW {fast} \
415. CONFIG.PCW_MIO_31_DIRECTION {inout} \
416. CONFIG.PCW_MIO_31_IOTYPE {LVCMOS 1.8V} \
417. CONFIG.PCW_MIO_31_PULLUP {enabled} \
418. CONFIG.PCW_MIO_31_SLEW {fast} \
419. CONFIG.PCW_MIO_32_DIRECTION {inout} \
420. CONFIG.PCW_MIO_32_IOTYPE {LVCMOS 1.8V} \
421. CONFIG.PCW_MIO_32_PULLUP {enabled} \
422. CONFIG.PCW_MIO_32_SLEW {fast} \
423. CONFIG.PCW_MIO_33_DIRECTION {inout} \
424. CONFIG.PCW_MIO_33_IOTYPE {LVCMOS 1.8V} \
425. CONFIG.PCW_MIO_33_PULLUP {enabled} \
426. CONFIG.PCW_MIO_33_SLEW {fast} \
427. CONFIG.PCW_MIO_34_DIRECTION {inout} \
428. CONFIG.PCW_MIO_34_IOTYPE {LVCMOS 1.8V} \
429. CONFIG.PCW_MIO_34_PULLUP {enabled} \
430. CONFIG.PCW_MIO_34_SLEW {fast} \
431. CONFIG.PCW_MIO_35_DIRECTION {inout} \
432. CONFIG.PCW_MIO_35_IOTYPE {LVCMOS 1.8V} \
433. CONFIG.PCW_MIO_35_PULLUP {enabled} \
434. CONFIG.PCW_MIO_35_SLEW {fast} \
435. CONFIG.PCW_MIO_36_DIRECTION {inout} \
436. CONFIG.PCW_MIO_36_IOTYPE {LVCMOS 1.8V} \
437. CONFIG.PCW_MIO_36_PULLUP {enabled} \
438. CONFIG.PCW_MIO_36_SLEW {fast} \
439. CONFIG.PCW_MIO_37_DIRECTION {inout} \
440. CONFIG.PCW_MIO_37_IOTYPE {LVCMOS 1.8V} \
441. CONFIG.PCW_MIO_37_PULLUP {enabled} \
442. CONFIG.PCW_MIO_37_SLEW {fast} \
443. CONFIG.PCW_MIO_38_DIRECTION {inout} \
444. CONFIG.PCW_MIO_38_IOTYPE {LVCMOS 1.8V} \
445. CONFIG.PCW_MIO_38_PULLUP {enabled} \
446. CONFIG.PCW_MIO_38_SLEW {fast} \
447. CONFIG.PCW_MIO_39_DIRECTION {inout} \
448. CONFIG.PCW_MIO_39_IOTYPE {LVCMOS 1.8V} \
449. CONFIG.PCW_MIO_39_PULLUP {enabled} \
450. CONFIG.PCW_MIO_39_SLEW {fast} \
451. CONFIG.PCW_MIO_3_DIRECTION {inout} \
452. CONFIG.PCW_MIO_3_IOTYPE {LVCMOS 3.3V} \
453. CONFIG.PCW_MIO_3_PULLUP {disabled} \
454. CONFIG.PCW_MIO_3_SLEW {slow} \
455. CONFIG.PCW_MIO_40_DIRECTION {inout} \
456. CONFIG.PCW_MIO_40_IOTYPE {LVCMOS 1.8V} \
457. CONFIG.PCW_MIO_40_PULLUP {enabled} \
458. CONFIG.PCW_MIO_40_SLEW {slow} \
459. CONFIG.PCW_MIO_41_DIRECTION {inout} \
460. CONFIG.PCW_MIO_41_IOTYPE {LVCMOS 1.8V} \
461. CONFIG.PCW_MIO_41_PULLUP {enabled} \
462. CONFIG.PCW_MIO_41_SLEW {slow} \
463. CONFIG.PCW_MIO_42_DIRECTION {inout} \
464. CONFIG.PCW_MIO_42_IOTYPE {LVCMOS 1.8V} \
465. CONFIG.PCW_MIO_42_PULLUP {enabled} \
466. CONFIG.PCW_MIO_42_SLEW {slow} \
467. CONFIG.PCW_MIO_43_DIRECTION {inout} \
468. CONFIG.PCW_MIO_43_IOTYPE {LVCMOS 1.8V} \
469. CONFIG.PCW_MIO_43_PULLUP {enabled} \
470. CONFIG.PCW_MIO_43_SLEW {slow} \
471. CONFIG.PCW_MIO_44_DIRECTION {inout} \
472. CONFIG.PCW_MIO_44_IOTYPE {LVCMOS 1.8V} \
473. CONFIG.PCW_MIO_44_PULLUP {enabled} \
474. CONFIG.PCW_MIO_44_SLEW {slow} \
475. CONFIG.PCW_MIO_45_DIRECTION {inout} \
476. CONFIG.PCW_MIO_45_IOTYPE {LVCMOS 1.8V} \
477. CONFIG.PCW_MIO_45_PULLUP {enabled} \
478. CONFIG.PCW_MIO_45_SLEW {slow} \
479. CONFIG.PCW_MIO_46_DIRECTION {out} \
480. CONFIG.PCW_MIO_46_IOTYPE {LVCMOS 1.8V} \
481. CONFIG.PCW_MIO_46_PULLUP {enabled} \
482. CONFIG.PCW_MIO_46_SLEW {slow} \
483. CONFIG.PCW_MIO_47_DIRECTION {in} \
484. CONFIG.PCW_MIO_47_IOTYPE {LVCMOS 1.8V} \
485. CONFIG.PCW_MIO_47_PULLUP {enabled} \
486. CONFIG.PCW_MIO_47_SLEW {slow} \
487. CONFIG.PCW_MIO_48_DIRECTION {out} \
488. CONFIG.PCW_MIO_48_IOTYPE {LVCMOS 1.8V} \
489. CONFIG.PCW_MIO_48_PULLUP {enabled} \
490. CONFIG.PCW_MIO_48_SLEW {slow} \
491. CONFIG.PCW_MIO_49_DIRECTION {in} \
492. CONFIG.PCW_MIO_49_IOTYPE {LVCMOS 1.8V} \
493. CONFIG.PCW_MIO_49_PULLUP {enabled} \
494. CONFIG.PCW_MIO_49_SLEW {slow} \
495. CONFIG.PCW_MIO_4_DIRECTION {inout} \
496. CONFIG.PCW_MIO_4_IOTYPE {LVCMOS 3.3V} \
497. CONFIG.PCW_MIO_4_PULLUP {disabled} \
498. CONFIG.PCW_MIO_4_SLEW {slow} \
499. CONFIG.PCW_MIO_50_DIRECTION {inout} \
500. CONFIG.PCW_MIO_50_IOTYPE {LVCMOS 1.8V} \
501. CONFIG.PCW_MIO_50_PULLUP {enabled} \
502. CONFIG.PCW_MIO_50_SLEW {slow} \
503. CONFIG.PCW_MIO_51_DIRECTION {inout} \
504. CONFIG.PCW_MIO_51_IOTYPE {LVCMOS 1.8V} \
505. CONFIG.PCW_MIO_51_PULLUP {enabled} \
506. CONFIG.PCW_MIO_51_SLEW {slow} \
507. CONFIG.PCW_MIO_52_DIRECTION {out} \
508. CONFIG.PCW_MIO_52_IOTYPE {LVCMOS 1.8V} \
509. CONFIG.PCW_MIO_52_PULLUP {enabled} \
510. CONFIG.PCW_MIO_52_SLEW {slow} \
511. CONFIG.PCW_MIO_53_DIRECTION {inout} \
512. CONFIG.PCW_MIO_53_IOTYPE {LVCMOS 1.8V} \
513. CONFIG.PCW_MIO_53_PULLUP {enabled} \
514. CONFIG.PCW_MIO_53_SLEW {slow} \
515. CONFIG.PCW_MIO_5_DIRECTION {inout} \
516. CONFIG.PCW_MIO_5_IOTYPE {LVCMOS 3.3V} \
517. CONFIG.PCW_MIO_5_PULLUP {disabled} \
518. CONFIG.PCW_MIO_5_SLEW {slow} \
519. CONFIG.PCW_MIO_6_DIRECTION {out} \
520. CONFIG.PCW_MIO_6_IOTYPE {LVCMOS 3.3V} \
521. CONFIG.PCW_MIO_6_PULLUP {disabled} \
522. CONFIG.PCW_MIO_6_SLEW {slow} \
523. CONFIG.PCW_MIO_7_DIRECTION {out} \
524. CONFIG.PCW_MIO_7_IOTYPE {LVCMOS 3.3V} \
525. CONFIG.PCW_MIO_7_PULLUP {disabled} \
526. CONFIG.PCW_MIO_7_SLEW {slow} \
527. CONFIG.PCW_MIO_8_DIRECTION {out} \
528. CONFIG.PCW_MIO_8_IOTYPE {LVCMOS 3.3V} \
529. CONFIG.PCW_MIO_8_PULLUP {disabled} \
530. CONFIG.PCW_MIO_8_SLEW {slow} \
531. CONFIG.PCW_MIO_9_DIRECTION {inout} \
532. CONFIG.PCW_MIO_9_IOTYPE {LVCMOS 3.3V} \
533. CONFIG.PCW_MIO_9_PULLUP {enabled} \
534. CONFIG.PCW_MIO_9_SLEW {slow} \
535. CONFIG.PCW_MIO_TREE_PERIPHERALS {GPIO#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#GPIO#Quad SPI Flash#GPIO#GPIO#GPIO#I2C 1#I2C 1#I2C 0#I2C 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#UART 1#UART 1#GPIO#GPIO#Enet 0#Enet 0} \
536. CONFIG.PCW_MIO_TREE_SIGNALS {gpio⁰#qspi0_ss_b#qspi0_io⁰#qspi0_io¹#qspi0_io²#qspi0_io³/HOLD_B#qspi0_sclk#gpio⁷#qspi_fbclk#gpio⁹#gpio¹⁰#gpio¹¹#scl#sda#scl#sda#tx_clk#txd⁰#txd¹#txd²#txd³#tx_ctl#rx_clk#rxd⁰#rxd¹#rxd²#rxd³#rx_ctl#gpio²⁸#gpio²⁹#gpio³⁰#gpio³¹#gpio³²#gpio³³#gpio³⁴#gpio³⁵#gpio³⁶#gpio³⁷#gpio³⁸#gpio³⁹#gpio⁴⁰#gpio⁴¹#gpio⁴²#gpio⁴³#gpio⁴⁴#gpio⁴⁵#gpio⁴⁶#gpio⁴⁷#tx#rx#gpio⁵⁰#gpio⁵¹#mdc#mdio} \
537. CONFIG.PCW_NAND_GRP_D8_ENABLE {0} \
538. CONFIG.PCW_NAND_PERIPHERAL_ENABLE {0} \
539. CONFIG.PCW_NOR_GRP_A25_ENABLE {0} \
540. CONFIG.PCW_NOR_GRP_CS0_ENABLE {0} \
541. CONFIG.PCW_NOR_GRP_CS1_ENABLE {0} \
542. CONFIG.PCW_NOR_GRP_SRAM_CS0_ENABLE {0} \
543. CONFIG.PCW_NOR_GRP_SRAM_CS1_ENABLE {0} \
544. CONFIG.PCW_NOR_GRP_SRAM_INT_ENABLE {0} \
545. CONFIG.PCW_NOR_PERIPHERAL_ENABLE {0} \
546. CONFIG.PCW_OVERRIDE_BASIC_CLOCK {0} \
547. CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY0 {0.221} \
548. CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY1 {0.222} \
549. CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY2 {0.217} \
550. CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY3 {0.244} \
551. CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_0 {-0.050} \
552. CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_1 {-0.044} \
553. CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_2 {-0.035} \
554. CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_3 {-0.100} \
555. CONFIG.PCW_PCAP_PERIPHERAL_CLKSRC {IO PLL} \
556. CONFIG.PCW_PCAP_PERIPHERAL_DIVISOR0 {5} \
557. CONFIG.PCW_PCAP_PERIPHERAL_FREQMHZ {200} \
558. CONFIG.PCW_PJTAG_PERIPHERAL_ENABLE {0} \
559. CONFIG.PCW_PLL_BYPASSMODE_ENABLE {0} \
560. CONFIG.PCW_PRESET_BANK0_VOLTAGE {LVCMOS 3.3V} \
561. CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 1.8V} \
562. CONFIG.PCW_QSPI_GRP_FBCLK_ENABLE {1} \
563. CONFIG.PCW_QSPI_GRP_FBCLK_IO {MIO 8} \
564. CONFIG.PCW_QSPI_GRP_IO1_ENABLE {0} \
565. CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE {1} \
566. CONFIG.PCW_QSPI_GRP_SINGLE_SS_IO {MIO 1 .. 6} \
567. CONFIG.PCW_QSPI_GRP_SS1_ENABLE {0} \
568. CONFIG.PCW_QSPI_INTERNAL_HIGHADDRESS {0xFCFFFFFF} \
569. CONFIG.PCW_QSPI_PERIPHERAL_CLKSRC {IO PLL} \
570. CONFIG.PCW_QSPI_PERIPHERAL_DIVISOR0 {5} \
571. CONFIG.PCW_QSPI_PERIPHERAL_ENABLE {1} \
572. CONFIG.PCW_QSPI_PERIPHERAL_FREQMHZ {200} \
573. CONFIG.PCW_QSPI_QSPI_IO {MIO 1 .. 6} \
574. CONFIG.PCW_SD0_GRP_CD_ENABLE {0} \
575. CONFIG.PCW_SD0_GRP_CD_IO {<Select>} \
576. CONFIG.PCW_SD0_GRP_POW_ENABLE {0} \
577. CONFIG.PCW_SD0_GRP_WP_ENABLE {0} \
578. CONFIG.PCW_SD0_PERIPHERAL_ENABLE {0} \
579. CONFIG.PCW_SD0_SD0_IO {<Select>} \
580. CONFIG.PCW_SDIO_PERIPHERAL_CLKSRC {IO PLL} \
581. CONFIG.PCW_SDIO_PERIPHERAL_DIVISOR0 {1} \
582. CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ {50} \
583. CONFIG.PCW_SDIO_PERIPHERAL_VALID {0} \
584. CONFIG.PCW_SINGLE_QSPI_DATA_MODE {x4} \
585. CONFIG.PCW_SMC_PERIPHERAL_CLKSRC {IO PLL} \
586. CONFIG.PCW_SMC_PERIPHERAL_DIVISOR0 {1} \
587. CONFIG.PCW_SMC_PERIPHERAL_FREQMHZ {100} \
588. CONFIG.PCW_SPI_PERIPHERAL_DIVISOR0 {1} \
589. CONFIG.PCW_TPIU_PERIPHERAL_CLKSRC {External} \
590. CONFIG.PCW_TPIU_PERIPHERAL_DIVISOR0 {1} \
591. CONFIG.PCW_TPIU_PERIPHERAL_FREQMHZ {200} \
592. CONFIG.PCW_UART1_BAUD_RATE {115200} \
593. CONFIG.PCW_UART1_GRP_FULL_ENABLE {0} \
594. CONFIG.PCW_UART1_PERIPHERAL_ENABLE {1} \
595. CONFIG.PCW_UART1_UART1_IO {MIO 48 .. 49} \
596. CONFIG.PCW_UART_PERIPHERAL_CLKSRC {IO PLL} \
597. CONFIG.PCW_UART_PERIPHERAL_DIVISOR0 {10} \
598. CONFIG.PCW_UART_PERIPHERAL_FREQMHZ {100} \
599. CONFIG.PCW_UART_PERIPHERAL_VALID {1} \
600. CONFIG.PCW_UIPARAM_ACT_DDR_FREQ_MHZ {533.333374} \
601. CONFIG.PCW_UIPARAM_DDR_ADV_ENABLE {0} \
602. CONFIG.PCW_UIPARAM_DDR_AL {0} \
603. CONFIG.PCW_UIPARAM_DDR_BANK_ADDR_COUNT {3} \
604. CONFIG.PCW_UIPARAM_DDR_BL {8} \
605. CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0 {0.221} \
606. CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1 {0.222} \
607. CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2 {0.217} \
608. CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3 {0.244} \
609. CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH {32 Bit} \
610. CONFIG.PCW_UIPARAM_DDR_CL {7} \
611. CONFIG.PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM {18.8} \
612. CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH {80.4535} \
613. CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY {160} \
614. CONFIG.PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM {18.8} \
615. CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH {80.4535} \
616. CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY {160} \
617. CONFIG.PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM {18.8} \
618. CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH {80.4535} \
619. CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY {160} \
620. CONFIG.PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM {18.8} \
621. CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH {80.4535} \
622. CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY {160} \
623. CONFIG.PCW_UIPARAM_DDR_CLOCK_STOP_EN {0} \
624. CONFIG.PCW_UIPARAM_DDR_COL_ADDR_COUNT {10} \
625. CONFIG.PCW_UIPARAM_DDR_CWL {6} \
626. CONFIG.PCW_UIPARAM_DDR_DEVICE_CAPACITY {4096 MBits} \
627. CONFIG.PCW_UIPARAM_DDR_DQS_0_LENGTH_MM {22.8} \
628. CONFIG.PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH {105.056} \
629. CONFIG.PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY {160} \
630. CONFIG.PCW_UIPARAM_DDR_DQS_1_LENGTH_MM {27.9} \
631. CONFIG.PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH {66.904} \
632. CONFIG.PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY {160} \
633. CONFIG.PCW_UIPARAM_DDR_DQS_2_LENGTH_MM {22.9} \
634. CONFIG.PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH {89.1715} \
635. CONFIG.PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY {160} \
636. CONFIG.PCW_UIPARAM_DDR_DQS_3_LENGTH_MM {29.4} \
637. CONFIG.PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH {113.63} \
638. CONFIG.PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY {160} \
639. CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 {-0.050} \
640. CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 {-0.044} \
641. CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 {-0.035} \
642. CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 {-0.100} \
643. CONFIG.PCW_UIPARAM_DDR_DQ_0_LENGTH_MM {22.8} \
644. CONFIG.PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH {98.503} \
645. CONFIG.PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY {160} \
646. CONFIG.PCW_UIPARAM_DDR_DQ_1_LENGTH_MM {27.9} \
647. CONFIG.PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH {68.5855} \
648. CONFIG.PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY {160} \
649. CONFIG.PCW_UIPARAM_DDR_DQ_2_LENGTH_MM {22.9} \
650. CONFIG.PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH {90.295} \
651. CONFIG.PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY {160} \
652. CONFIG.PCW_UIPARAM_DDR_DQ_3_LENGTH_MM {29.4} \
653. CONFIG.PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH {103.977} \
654. CONFIG.PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY {160} \
655. CONFIG.PCW_UIPARAM_DDR_DRAM_WIDTH {16 Bits} \
656. CONFIG.PCW_UIPARAM_DDR_ECC {Disabled} \
657. CONFIG.PCW_UIPARAM_DDR_ENABLE {1} \
658. CONFIG.PCW_UIPARAM_DDR_FREQ_MHZ {533.333333} \
659. CONFIG.PCW_UIPARAM_DDR_HIGH_TEMP {Normal (0-85)} \
660. CONFIG.PCW_UIPARAM_DDR_MEMORY_TYPE {DDR 3 (Low Voltage)} \
661. CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41K256M16 RE-125} \
662. CONFIG.PCW_UIPARAM_DDR_ROW_ADDR_COUNT {15} \
663. CONFIG.PCW_UIPARAM_DDR_SPEED_BIN {DDR3_1066F} \
664. CONFIG.PCW_UIPARAM_DDR_TRAIN_DATA_EYE {1} \
665. CONFIG.PCW_UIPARAM_DDR_TRAIN_READ_GATE {1} \
666. CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL {1} \
667. CONFIG.PCW_UIPARAM_DDR_T_FAW {40.0} \
668. CONFIG.PCW_UIPARAM_DDR_T_RAS_MIN {35.0} \
669. CONFIG.PCW_UIPARAM_DDR_T_RC {48.75} \
670. CONFIG.PCW_UIPARAM_DDR_T_RCD {7} \
671. CONFIG.PCW_UIPARAM_DDR_T_RP {7} \
672. CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF {0} \
673. CONFIG.PCW_USB0_PERIPHERAL_ENABLE {0} \
674. CONFIG.PCW_USB0_PERIPHERAL_FREQMHZ {60} \
675. CONFIG.PCW_USB0_RESET_ENABLE {1} \
676. CONFIG.PCW_USB0_RESET_IO {MIO 46} \
677. CONFIG.PCW_USB0_USB0_IO {<Select>} \
678. CONFIG.PCW_USB1_RESET_ENABLE {0} \
679. CONFIG.PCW_USB_RESET_ENABLE {1} \
680. CONFIG.PCW_USB_RESET_POLARITY {Active Low} \
681. CONFIG.PCW_USB_RESET_SELECT {<Select>} \
682. CONFIG.PCW_USE_AXI_NONSECURE {0} \
683. CONFIG.PCW_USE_CROSS_TRIGGER {0} \
684. CONFIG.PCW_USE_M_AXI_GP0 {0} \
685. ] $processing_system7_0
687. # Create interface connections
688. connect_bd_intf_net -intf_net processing_system7_0_DDR [get_bd_intf_ports DDR] [get_bd_intf_pins processing_system7_0/DDR]
689. connect_bd_intf_net -intf_net processing_system7_0_FIXED_IO [get_bd_intf_ports FIXED_IO] [get_bd_intf_pins processing_system7_0/FIXED_IO]
690. connect_bd_intf_net -intf_net processing_system7_0_GPIO_0 [get_bd_intf_ports GPIO_0_0] [get_bd_intf_pins processing_system7_0/GPIO_0]
692. # Create port connections
694. # Create address segments
696. # Perform GUI Layout
697. regenerate_bd_layout -layout_string {
698. "ActiveEmotionalView":"Default View",
699. "Default View_ScaleFactor":"1.0",
700. "Default View_TopLeft":"-337,-352",
701. "ExpandedHierarchyInLayout":"",
702. "guistr":"# # String gsaved with Nlview 7.0r6 2020-01-29 bk=1.5227 VDI=41 GEI=36 GUI=JA:10.0 non-TLS
703. # -string -flagsOSRD
704. preplace port DDR -pg 1 -lvl 2 -x 430 -y -120 -defaultsOSRD
705. preplace port FIXED_IO -pg 1 -lvl 2 -x 430 -y -100 -defaultsOSRD
706. preplace port GPIO_0_0 -pg 1 -lvl 2 -x 430 -y -140 -defaultsOSRD
707. preplace inst processing_system7_0 -pg 1 -lvl 1 -x 210 -y -100 -defaultsOSRD
708. preplace netloc processing_system7_0_GPIO_0 1 1 1 N -140
709. preplace netloc processing_system7_0_FIXED_IO 1 1 1 NJ -100
710. preplace netloc processing_system7_0_DDR 1 1 1 NJ -120
711. levelinfo -pg 1 0 210 430
712. pagesize -pg 1 -db -bbox -sgen 0 -220 550 200
713. "
714. }
716. # Restore current instance
717. current_bd_instance $oldCurInst
719. validate_bd_design
720. save_bd_design
721. close_bd_design $design_name
722. }
723. cr_bd_design_1 ""
     INFO: [BD::TCL 103-2010] Currently there is no design <design_1> in project, so creating one...
     Wrote : <C:\AimaginProjects\Zybo\Hardware_Z7000\i2c_demo_new_20230315\project_1\project_1.srcs\sources_1\bd\design_1\design_1.bd>
     create_bd_design: Time (s): cpu = 00:00:04 ; elapsed = 00:00:07 . Memory (MB): peak = 1115.910 ; gain = 0.000
     INFO: [BD::TCL 103-2011] Checking if the following IPs exist in the project's IP catalog:
     xilinx.com:ip:processing_system7:5.5 .
     CRITICAL WARNING: [PSU-1] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.050 . PS DDR interfaces might fail when entering negative DQS skew values.
     CRITICAL WARNING: [PSU-2] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.044 . PS DDR interfaces might fail when entering negative DQS skew values.
     CRITICAL WARNING: [PSU-3] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 has negative value -0.035 . PS DDR interfaces might fail when entering negative DQS skew values.
     CRITICAL WARNING: [PSU-4] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 has negative value -0.100 . PS DDR interfaces might fail when entering negative DQS skew values.
     CRITICAL WARNING: [PSU-1] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.050 . PS DDR interfaces might fail when entering negative DQS skew values.
     CRITICAL WARNING: [PSU-2] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.044 . PS DDR interfaces might fail when entering negative DQS skew values.
     CRITICAL WARNING: [PSU-3] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 has negative value -0.035 . PS DDR interfaces might fail when entering negative DQS skew values.
     CRITICAL WARNING: [PSU-4] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 has negative value -0.100 . PS DDR interfaces might fail when entering negative DQS skew values.
     Wrote : <C:\AimaginProjects\Zybo\Hardware_Z7000\i2c_demo_new_20230315\project_1\project_1.srcs\sources_1\bd\design_1\design_1.bd>
     Wrote : <C:/AimaginProjects/Zybo/Hardware_Z7000/i2c_demo_new_20230315/project_1/project_1.srcs/sources_1/bd/design_1/ui/bd_1f5defd0.ui>
724. set_property REGISTERED_WITH_MANAGER "1" [get_files design_1.bd ]
725. set_property SYNTH_CHECKPOINT_MODE "Hierarchical" [get_files design_1.bd ]
726. if { [get_property IS_LOCKED [ get_files -norecurse design_1.bd] ] == 1 } {
727. import_files -fileset sources_1 [file normalize "${origin_dir}/project_1/project_1.gen/sources_1/bd/design_1/hdl/design_1_wrapper.vhd" ]
728. } else {
729. set wrapper_path [make_wrapper -fileset sources_1 -files [ get_files -norecurse design_1.bd] -top]
730. add_files -norecurse -fileset sources_1 $wrapper_path
731. }
     INFO: [BD 41-1662] The design 'design_1.bd' is already validated. Therefore parameter propagation will not be re-run.
     VHDL Output written to : c:/AimaginProjects/Zybo/Hardware_Z7000/i2c_demo_new_20230315/project_1/project_1.gen/sources_1/bd/design_1/synth/design_1.vhd
     VHDL Output written to : c:/AimaginProjects/Zybo/Hardware_Z7000/i2c_demo_new_20230315/project_1/project_1.gen/sources_1/bd/design_1/sim/design_1.vhd
     VHDL Output written to : c:/AimaginProjects/Zybo/Hardware_Z7000/i2c_demo_new_20230315/project_1/project_1.gen/sources_1/bd/design_1/hdl/design_1_wrapper.vhd
     make_wrapper: Time (s): cpu = 00:00:01 ; elapsed = 00:00:06 . Memory (MB): peak = 1400.250 ; gain = 138.207
732. if {[string equal [get_runs -quiet synth_1] ""]} {
733. create_run -name synth_1 -part xc7z020clg400-1 -flow {Vivado Synthesis 2020} -strategy "Vivado Synthesis Defaults" -report_strategy {No Reports} -constrset constrs_1
734. } else {
735. set_property strategy "Vivado Synthesis Defaults" [get_runs synth_1]
736. set_property flow "Vivado Synthesis 2020" [get_runs synth_1]
737. }
738. set obj [get_runs synth_1]
739. set_property set_report_strategy_name 1 $obj
740. set_property report_strategy {Vivado Synthesis Default Reports} $obj
741. set_property set_report_strategy_name 0 $obj
742. if { [ string equal [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0] "" ] } {
743. create_report_config -report_name synth_1_synth_report_utilization_0 -report_type report_utilization:1.0 -steps synth_design -runs synth_1
744. }
745. set obj [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0]
746. if { $obj != "" } {
748. }
749. set obj [get_runs synth_1]
750. set_property -name "strategy" -value "Vivado Synthesis Defaults" -objects $obj
751. current_run -synthesis [get_runs synth_1]
752. if {[string equal [get_runs -quiet impl_1] ""]} {
753. create_run -name impl_1 -part xc7z020clg400-1 -flow {Vivado Implementation 2020} -strategy "Vivado Implementation Defaults" -report_strategy {No Reports} -constrset constrs_1 -parent_run synth_1
754. } else {
755. set_property strategy "Vivado Implementation Defaults" [get_runs impl_1]
756. set_property flow "Vivado Implementation 2020" [get_runs impl_1]
757. }
758. set obj [get_runs impl_1]
759. set_property set_report_strategy_name 1 $obj
760. set_property report_strategy {Vivado Implementation Default Reports} $obj
761. set_property set_report_strategy_name 0 $obj
762. if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0] "" ] } {
763. create_report_config -report_name impl_1_init_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps init_design -runs impl_1
764. }
765. set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0]
766. if { $obj != "" } {
767. set_property -name "is_enabled" -value "0" -objects $obj
768. set_property -name "options.max_paths" -value "10" -objects $obj
770. }
771. if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0] "" ] } {
772. create_report_config -report_name impl_1_opt_report_drc_0 -report_type report_drc:1.0 -steps opt_design -runs impl_1
773. }
774. set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0]
775. if { $obj != "" } {
777. }
778. if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0] "" ] } {
779. create_report_config -report_name impl_1_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps opt_design -runs impl_1
780. }
781. set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0]
782. if { $obj != "" } {
783. set_property -name "is_enabled" -value "0" -objects $obj
784. set_property -name "options.max_paths" -value "10" -objects $obj
786. }
787. if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0] "" ] } {
788. create_report_config -report_name impl_1_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps power_opt_design -runs impl_1
789. }
790. set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0]
791. if { $obj != "" } {
792. set_property -name "is_enabled" -value "0" -objects $obj
793. set_property -name "options.max_paths" -value "10" -objects $obj
795. }
796. if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0] "" ] } {
797. create_report_config -report_name impl_1_place_report_io_0 -report_type report_io:1.0 -steps place_design -runs impl_1
798. }
799. set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0]
800. if { $obj != "" } {
802. }
803. if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0] "" ] } {
804. create_report_config -report_name impl_1_place_report_utilization_0 -report_type report_utilization:1.0 -steps place_design -runs impl_1
805. }
806. set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0]
807. if { $obj != "" } {
809. }
810. if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0] "" ] } {
811. create_report_config -report_name impl_1_place_report_control_sets_0 -report_type report_control_sets:1.0 -steps place_design -runs impl_1
812. }
813. set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0]
814. if { $obj != "" } {
815. set_property -name "options.verbose" -value "1" -objects $obj
817. }
818. if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0] "" ] } {
819. create_report_config -report_name impl_1_place_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1
820. }
821. set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0]
822. if { $obj != "" } {
823. set_property -name "is_enabled" -value "0" -objects $obj
825. }
826. if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1] "" ] } {
827. create_report_config -report_name impl_1_place_report_incremental_reuse_1 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1
828. }
829. set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1]
830. if { $obj != "" } {
831. set_property -name "is_enabled" -value "0" -objects $obj
833. }
834. if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0] "" ] } {
835. create_report_config -report_name impl_1_place_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps place_design -runs impl_1
836. }
837. set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0]
838. if { $obj != "" } {
839. set_property -name "is_enabled" -value "0" -objects $obj
840. set_property -name "options.max_paths" -value "10" -objects $obj
842. }
843. if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0] "" ] } {
844. create_report_config -report_name impl_1_post_place_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_place_power_opt_design -runs impl_1
845. }
846. set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0]
847. if { $obj != "" } {
848. set_property -name "is_enabled" -value "0" -objects $obj
849. set_property -name "options.max_paths" -value "10" -objects $obj
851. }
852. if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0] "" ] } {
853. create_report_config -report_name impl_1_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps phys_opt_design -runs impl_1
854. }
855. set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0]
856. if { $obj != "" } {
857. set_property -name "is_enabled" -value "0" -objects $obj
858. set_property -name "options.max_paths" -value "10" -objects $obj
860. }
861. if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0] "" ] } {
862. create_report_config -report_name impl_1_route_report_drc_0 -report_type report_drc:1.0 -steps route_design -runs impl_1
863. }
864. set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0]
865. if { $obj != "" } {
867. }
868. if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0] "" ] } {
869. create_report_config -report_name impl_1_route_report_methodology_0 -report_type report_methodology:1.0 -steps route_design -runs impl_1
870. }
871. set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0]
872. if { $obj != "" } {
874. }
875. if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0] "" ] } {
876. create_report_config -report_name impl_1_route_report_power_0 -report_type report_power:1.0 -steps route_design -runs impl_1
877. }
878. set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0]
879. if { $obj != "" } {
881. }
882. if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0] "" ] } {
883. create_report_config -report_name impl_1_route_report_route_status_0 -report_type report_route_status:1.0 -steps route_design -runs impl_1
884. }
885. set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0]
886. if { $obj != "" } {
888. }
889. if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0] "" ] } {
890. create_report_config -report_name impl_1_route_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps route_design -runs impl_1
891. }
892. set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0]
893. if { $obj != "" } {
894. set_property -name "options.max_paths" -value "10" -objects $obj
896. }
897. if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0] "" ] } {
898. create_report_config -report_name impl_1_route_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps route_design -runs impl_1
899. }
900. set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0]
901. if { $obj != "" } {
903. }
904. if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0] "" ] } {
905. create_report_config -report_name impl_1_route_report_clock_utilization_0 -report_type report_clock_utilization:1.0 -steps route_design -runs impl_1
906. }
907. set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0]
908. if { $obj != "" } {
910. }
911. if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0] "" ] } {
912. create_report_config -report_name impl_1_route_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps route_design -runs impl_1
913. }
914. set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0]
915. if { $obj != "" } {
916. set_property -name "options.warn_on_violation" -value "1" -objects $obj
918. }
919. if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0] "" ] } {
920. create_report_config -report_name impl_1_post_route_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_route_phys_opt_design -runs impl_1
921. }
922. set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0]
923. if { $obj != "" } {
924. set_property -name "options.max_paths" -value "10" -objects $obj
925. set_property -name "options.warn_on_violation" -value "1" -objects $obj
927. }
928. if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0] "" ] } {
929. create_report_config -report_name impl_1_post_route_phys_opt_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps post_route_phys_opt_design -runs impl_1
930. }
931. set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0]
932. if { $obj != "" } {
933. set_property -name "options.warn_on_violation" -value "1" -objects $obj
935. }
936. set obj [get_runs impl_1]
937. set_property -name "strategy" -value "Vivado Implementation Defaults" -objects $obj
938. set_property -name "steps.write_bitstream.args.readback_file" -value "0" -objects $obj
939. set_property -name "steps.write_bitstream.args.verbose" -value "0" -objects $obj
940. current_run -implementation [get_runs impl_1]
941. puts "INFO: Project created:${_xil_proj_name_}"
     INFO: Project created:project_1
942. if {[string equal [get_dashboard_gadgets [ list "drc_1" ] ] ""]} {
943. create_dashboard_gadget -name {drc_1} -type drc
944. }
945. set obj [get_dashboard_gadgets [ list "drc_1" ] ]
946. set_property -name "reports" -value "impl_1#impl_1_route_report_drc_0" -objects $obj
947. if {[string equal [get_dashboard_gadgets [ list "methodology_1" ] ] ""]} {
948. create_dashboard_gadget -name {methodology_1} -type methodology
949. }
950. set obj [get_dashboard_gadgets [ list "methodology_1" ] ]
951. set_property -name "reports" -value "impl_1#impl_1_route_report_methodology_0" -objects $obj
952. if {[string equal [get_dashboard_gadgets [ list "power_1" ] ] ""]} {
953. create_dashboard_gadget -name {power_1} -type power
954. }
955. set obj [get_dashboard_gadgets [ list "power_1" ] ]
956. set_property -name "reports" -value "impl_1#impl_1_route_report_power_0" -objects $obj
957. if {[string equal [get_dashboard_gadgets [ list "timing_1" ] ] ""]} {
958. create_dashboard_gadget -name {timing_1} -type timing
959. }
960. set obj [get_dashboard_gadgets [ list "timing_1" ] ]
961. set_property -name "reports" -value "impl_1#impl_1_route_report_timing_summary_0" -objects $obj
962. if {[string equal [get_dashboard_gadgets [ list "utilization_1" ] ] ""]} {
963. create_dashboard_gadget -name {utilization_1} -type utilization
964. }
965. set obj [get_dashboard_gadgets [ list "utilization_1" ] ]
966. set_property -name "reports" -value "synth_1#synth_1_synth_report_utilization_0" -objects $obj
967. set_property -name "run.step" -value "synth_design" -objects $obj
968. set_property -name "run.type" -value "synthesis" -objects $obj
969. if {[string equal [get_dashboard_gadgets [ list "utilization_2" ] ] ""]} {
970. create_dashboard_gadget -name {utilization_2} -type utilization
971. }
972. set obj [get_dashboard_gadgets [ list "utilization_2" ] ]
973. set_property -name "reports" -value "impl_1#impl_1_place_report_utilization_0" -objects $obj
974. move_dashboard_gadget -name {utilization_1} -row 0 -col 0
975. move_dashboard_gadget -name {power_1} -row 1 -col 0
976. move_dashboard_gadget -name {drc_1} -row 2 -col 0
977. move_dashboard_gadget -name {timing_1} -row 0 -col 1
978. move_dashboard_gadget -name {utilization_2} -row 1 -col 1
979. move_dashboard_gadget -name {methodology_1} -row 2 -col 1
     update_compile_order -fileset sources_1

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