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Cannot build hardware for i2c_demo

Added by Johan Henning 12 months ago

1. When executing the .tcl file a message is displayed that it cannot find the .xdc file. It seems that the .xdc file shall be moved two directories up
2. When executing the .tcl file (after moving the .xdc file) this message pops up: WARNING: [Vivado 12-9135] Ignoring repo path (C:/Users/admin/AppData/Roaming/Xilinx/Vivado/2020.2/xhub/board_store/xilinx_board_store) because it contains no board files
No block design is created.


Replies (6)

RE: Cannot build hardware for i2c_demo - Added by Shawn Sebastian Pulle (ฌอน) 12 months ago

Hi Johan,

Thank you for the feedback. These changes to the tcl file will be implemented in a future release.
It is strange that no block design is being created with the second warning. In our testing it did not stop the block design.

RE: Cannot build hardware for i2c_demo - Added by Johan Henning 12 months ago

Hello,

See below my logfiles. It might be a good idea that Aimagin creates a build / test PC with a clean installation of Vivado and the required board files to verify that the delivered software will work at their customers site.

This is the logfile when trying to build the hardware:

start_gui
cd C:/AimaginProjects/Zybo/Hardware_Z7000/i2c_demo
source i2c_demo.tcl
  1. proc checkRequiredFiles { origin_dir} {
  2. set status true
  3. set files [list \
  4. "C:/Aimagin/zynq7000_xilinx/Other-Board_Files/zyboz7_project/vivado/My_Zybo-Z7-Master.xdc" \
  5. ]
  6. foreach ifile $files {
  7. if { ![file isfile $ifile] } {
  8. puts " Could not find remote file $ifile "
  9. set status false
  10. }
  11. }
  12. return $status
  13. }
  14. set origin_dir "."
  15. if { [info exists ::origin_dir_loc] } {
  16. set origin_dir $::origin_dir_loc
  17. }
  18. set xil_proj_name "project_1"
  19. if { [info exists ::user_project_name] } {
  20. set xil_proj_name $::user_project_name
  21. }
  22. variable script_file
  23. set script_file "i2c_demo.tcl"
  24. proc print_help {} {
  25. variable script_file
  26. puts "\nDescription:"
  27. puts "Recreate a Vivado project from this script. The created project will be"
  28. puts "functionally equivalent to the original project for which this script was"
  29. puts "generated. The script contains commands for creating a project, filesets,"
  30. puts "runs, adding/importing sources and setting properties on various objects.\n"
  31. puts "Syntax:"
  32. puts "$script_file"
  33. puts "$script_file -tclargs \[--origin_dir <path>\]"
  34. puts "$script_file -tclargs \[--project_name <name>\]"
  35. puts "$script_file -tclargs \[--help\]\n"
  36. puts "Usage:"
  37. puts "Name Description"
  38. puts "-------------------------------------------------------------------------"
  39. puts "\[--origin_dir <path>\] Determine source file paths wrt this path. Default"
  40. puts " origin_dir path value is \".\", otherwise, the value"
  41. puts " that was set with the \"-paths_relative_to\" switch"
  42. puts " when this script was generated.\n"
  43. puts "\[--project_name <name>\] Create project with the specified name. Default"
  44. puts " name is the name of the project from where this"
  45. puts " script was generated.\n"
  46. puts "\[--help\] Print help information for this script"
  47. puts "-------------------------------------------------------------------------\n"
  48. exit 0
  49. }
  50. if { $::argc > 0 } {
  51. for {set i 0} {$i < $::argc} {incr i} {
  52. set option [string trim [lindex $::argv $i]]
  53. switch regexp - $option {
  54. "--origin_dir" { incr i; set origin_dir [lindex $::argv $i] }
  55. "--project_name" { incr i; set xil_proj_name [lindex $::argv $i] }
  56. "--help" { print_help }
  57. default {
  58. if { [regexp {^-} $option] } {
  59. puts "ERROR: Unknown option '$option' specified, please type '$script_file -tclargs --help' for usage info.\n"
  60. return 1
  61. }
  62. }
  63. }
  64. }
  65. }
  66. set orig_proj_dir "[file normalize "$origin_dir/project_1"]"
  67. set validate_required 0
  68. if { $validate_required } {
  69. if { [checkRequiredFiles $origin_dir] } {
  70. puts "Tcl file $script_file is valid. All files required for project creation is accesable. "
  71. } else {
  72. puts "Tcl file $script_file is not valid. Not all files required for project creation is accesable. "
  73. return
  74. }
  75. }
  76. create_project ${_xil_proj_name_} ./${_xil_proj_name_} -part xc7z020clg400-1
    INFO: [IP_Flow 19-234] Refreshing IP repositories
    INFO: [IP_Flow 19-1704] No user IP repositories specified
    INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2020.2/data/ip'.
    create_project: Time (s): cpu = 00:00:04 ; elapsed = 00:00:08 . Memory (MB): peak = 1119.531 ; gain = 0.000
  77. set proj_dir [get_property directory [current_project]]
  78. set obj [current_project]
  79. set_property -name "board_part_repo_paths" -value "[file normalize "$origin_dir/../../../../../../Users/admin/AppData/Roaming/Xilinx/Vivado/2020.2/xhub/board_store/xilinx_board_store"]" -objects $obj
    WARNING: [Vivado 12-9135] Ignoring repo path (C:/Users/admin/AppData/Roaming/Xilinx/Vivado/2020.2/xhub/board_store/xilinx_board_store) because it contains no board files
  80. set_property -name "board_part" -value "digilentinc.com:zybo-z7-20:part0:1.0" -objects $obj
  81. set_property -name "default_lib" -value "xil_defaultlib" -objects $obj
  82. set_property -name "enable_vhdl_2008" -value "1" -objects $obj
  83. set_property -name "ip_cache_permissions" -value "read write" -objects $obj
  84. set_property -name "ip_output_repo" -value "$proj_dir/${_xil_proj_name_}.cache/ip" -objects $obj
  85. set_property -name "mem.enable_memory_map_generation" -value "1" -objects $obj
  86. set_property -name "platform.board_id" -value "zybo-z7-20" -objects $obj
  87. set_property -name "sim.central_dir" -value "$proj_dir/${_xil_proj_name_}.ip_user_files" -objects $obj
  88. set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj
  89. set_property -name "simulator_language" -value "Mixed" -objects $obj
  90. set_property -name "target_language" -value "VHDL" -objects $obj
  91. if {[string equal [get_filesets -quiet sources_1] ""]} {
  92. create_fileset -srcset sources_1
  93. }
  94. set obj [get_filesets sources_1]
  95. set obj [get_filesets sources_1]
  96. set_property -name "top" -value "design_1_wrapper" -objects $obj
  97. if {[string equal [get_filesets -quiet constrs_1] ""]} {
  98. create_fileset -constrset constrs_1
  99. }
  100. set obj [get_filesets constrs_1]
  101. set file "[file normalize "$origin_dir/../My_Zybo-Z7-Master.xdc"]"
    ERROR: [Vivado 12-172] File or Directory 'C:/AimaginProjects/Zybo/Hardware_Z7000/My_Zybo-Z7-Master.xdc' does not exist

After copying the file My_Zybo-Z7-Master.xdc to a location two levels up in the directory tree this is the result (no block design is created):

source i2c_demo.tcl
  1. proc checkRequiredFiles { origin_dir} {
  2. set status true
  3. set files [list \
  4. "C:/Aimagin/zynq7000_xilinx/Other-Board_Files/zyboz7_project/vivado/My_Zybo-Z7-Master.xdc" \
  5. ]
  6. foreach ifile $files {
  7. if { ![file isfile $ifile] } {
  8. puts " Could not find remote file $ifile "
  9. set status false
  10. }
  11. }
  12. return $status
  13. }
  14. set origin_dir "."
  15. if { [info exists ::origin_dir_loc] } {
  16. set origin_dir $::origin_dir_loc
  17. }
  18. set xil_proj_name "project_1"
  19. if { [info exists ::user_project_name] } {
  20. set xil_proj_name $::user_project_name
  21. }
  22. variable script_file
  23. set script_file "i2c_demo.tcl"
  24. proc print_help {} {
  25. variable script_file
  26. puts "\nDescription:"
  27. puts "Recreate a Vivado project from this script. The created project will be"
  28. puts "functionally equivalent to the original project for which this script was"
  29. puts "generated. The script contains commands for creating a project, filesets,"
  30. puts "runs, adding/importing sources and setting properties on various objects.\n"
  31. puts "Syntax:"
  32. puts "$script_file"
  33. puts "$script_file -tclargs \[--origin_dir <path>\]"
  34. puts "$script_file -tclargs \[--project_name <name>\]"
  35. puts "$script_file -tclargs \[--help\]\n"
  36. puts "Usage:"
  37. puts "Name Description"
  38. puts "-------------------------------------------------------------------------"
  39. puts "\[--origin_dir <path>\] Determine source file paths wrt this path. Default"
  40. puts " origin_dir path value is \".\", otherwise, the value"
  41. puts " that was set with the \"-paths_relative_to\" switch"
  42. puts " when this script was generated.\n"
  43. puts "\[--project_name <name>\] Create project with the specified name. Default"
  44. puts " name is the name of the project from where this"
  45. puts " script was generated.\n"
  46. puts "\[--help\] Print help information for this script"
  47. puts "-------------------------------------------------------------------------\n"
  48. exit 0
  49. }
  50. if { $::argc > 0 } {
  51. for {set i 0} {$i < $::argc} {incr i} {
  52. set option [string trim [lindex $::argv $i]]
  53. switch regexp - $option {
  54. "--origin_dir" { incr i; set origin_dir [lindex $::argv $i] }
  55. "--project_name" { incr i; set xil_proj_name [lindex $::argv $i] }
  56. "--help" { print_help }
  57. default {
  58. if { [regexp {^-} $option] } {
  59. puts "ERROR: Unknown option '$option' specified, please type '$script_file -tclargs --help' for usage info.\n"
  60. return 1
  61. }
  62. }
  63. }
  64. }
  65. }
  66. set orig_proj_dir "[file normalize "$origin_dir/project_1"]"
  67. set validate_required 0
  68. if { $validate_required } {
  69. if { [checkRequiredFiles $origin_dir] } {
  70. puts "Tcl file $script_file is valid. All files required for project creation is accesable. "
  71. } else {
  72. puts "Tcl file $script_file is not valid. Not all files required for project creation is accesable. "
  73. return
  74. }
  75. }
  76. create_project ${_xil_proj_name_} ./${_xil_proj_name_} -part xc7z020clg400-1
    INFO: [IP_Flow 19-234] Refreshing IP repositories
    INFO: [IP_Flow 19-1704] No user IP repositories specified
    INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2020.2/data/ip'.
  77. set proj_dir [get_property directory [current_project]]
  78. set obj [current_project]
  79. set_property -name "board_part_repo_paths" -value "[file normalize "$origin_dir/../../../../../../Users/admin/AppData/Roaming/Xilinx/Vivado/2020.2/xhub/board_store/xilinx_board_store"]" -objects $obj
    WARNING: [Vivado 12-9135] Ignoring repo path (C:/Users/admin/AppData/Roaming/Xilinx/Vivado/2020.2/xhub/board_store/xilinx_board_store) because it contains no board files
  80. set_property -name "board_part" -value "digilentinc.com:zybo-z7-20:part0:1.0" -objects $obj
  81. set_property -name "default_lib" -value "xil_defaultlib" -objects $obj
  82. set_property -name "enable_vhdl_2008" -value "1" -objects $obj
  83. set_property -name "ip_cache_permissions" -value "read write" -objects $obj
  84. set_property -name "ip_output_repo" -value "$proj_dir/${_xil_proj_name_}.cache/ip" -objects $obj
  85. set_property -name "mem.enable_memory_map_generation" -value "1" -objects $obj
  86. set_property -name "platform.board_id" -value "zybo-z7-20" -objects $obj
  87. set_property -name "sim.central_dir" -value "$proj_dir/${_xil_proj_name_}.ip_user_files" -objects $obj
  88. set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj
  89. set_property -name "simulator_language" -value "Mixed" -objects $obj
  90. set_property -name "target_language" -value "VHDL" -objects $obj
  91. if {[string equal [get_filesets -quiet sources_1] ""]} {
  92. create_fileset -srcset sources_1
  93. }
  94. set obj [get_filesets sources_1]
  95. set obj [get_filesets sources_1]
  96. set_property -name "top" -value "design_1_wrapper" -objects $obj
  97. if {[string equal [get_filesets -quiet constrs_1] ""]} {
  98. create_fileset -constrset constrs_1
  99. }
  100. set obj [get_filesets constrs_1]
  101. set file "[file normalize "$origin_dir/../My_Zybo-Z7-Master.xdc"]"
  102. set file_added [add_files -norecurse -fileset $obj [list $file]]
  103. set file "$origin_dir/../My_Zybo-Z7-Master.xdc"
  104. set file [file normalize $file]
  105. set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]]
  106. set_property -name "file_type" -value "XDC" -objects $file_obj
  107. set obj [get_filesets constrs_1]
  108. if {[string equal [get_filesets -quiet sim_1] ""]} {
  109. create_fileset -simset sim_1
  110. }
  111. set obj [get_filesets sim_1]
  112. set obj [get_filesets sim_1]
  113. set_property -name "hbs.configure_design_for_hier_access" -value "1" -objects $obj
  114. set_property -name "top" -value "design_1_wrapper" -objects $obj
  115. set_property -name "top_lib" -value "xil_defaultlib" -objects $obj
  116. set obj [get_filesets utils_1]
  117. set obj [get_filesets utils_1]
  118. proc cr_bd_design_1 { parentCell } {
  119. # CHANGE DESIGN NAME HERE
  120. set design_name design_1
  121. common::send_gid_msg -ssname BD::TCL -id 2010 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..."
  122. create_bd_design $design_name
  123. set bCheckIPsPassed 1
  124. ##################################################################
  125. # CHECK IPs
  126. ##################################################################
  127. set bCheckIPs 1
  128. if { $bCheckIPs == 1 } {
  129. set list_check_ips "\
  130. xilinx.com:ip:processing_system7:5.5\
  131. "
  132. set list_ips_missing ""
  133. common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
  134. foreach ip_vlnv $list_check_ips {
  135. set ip_obj [get_ipdefs -all $ip_vlnv]
  136. if { $ip_obj eq "" } {
  137. lappend list_ips_missing $ip_vlnv
  138. }
  139. }
  140. if { $list_ips_missing ne "" } {
  141. catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP to the project." }
  142. set bCheckIPsPassed 0
  143. }
  144. }
  145. if { $bCheckIPsPassed != 1 } {
  146. common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above."
  147. return 3
  148. }
  149. variable script_folder
  150. if { $parentCell eq "" } {
  151. set parentCell [get_bd_cells /]
  152. }
  153. # Get object for parentCell
  154. set parentObj [get_bd_cells $parentCell]
  155. if { $parentObj == "" } {
  156. catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
  157. return
  158. }
  159. # Make sure parentObj is hier blk
  160. set parentType [get_property TYPE $parentObj]
  161. if { $parentType ne "hier" } {
  162. catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
  163. return
  164. }
  165. # Save current instance; Restore later
  166. set oldCurInst [current_bd_instance .]
  167. # Set parent object as current
  168. current_bd_instance $parentObj
  169. # Create interface ports
  170. set DDR [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR ]
  171. set FIXED_IO [ create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 FIXED_IO ]
  172. set GPIO_0_0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 GPIO_0_0 ]
  173. # Create ports
  174. # Create instance: processing_system7_0, and set properties
  175. set processing_system7_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0 ]
  176. set_property -dict [ list \
  177. CONFIG.PCW_ACT_APU_PERIPHERAL_FREQMHZ {666.666687} \
  178. CONFIG.PCW_ACT_CAN_PERIPHERAL_FREQMHZ {10.000000} \
  179. CONFIG.PCW_ACT_DCI_PERIPHERAL_FREQMHZ {10.158730} \
  180. CONFIG.PCW_ACT_ENET0_PERIPHERAL_FREQMHZ {125.000000} \
  181. CONFIG.PCW_ACT_ENET1_PERIPHERAL_FREQMHZ {10.000000} \
  182. CONFIG.PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ {50.000000} \
  183. CONFIG.PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ {10.000000} \
  184. CONFIG.PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ {10.000000} \
  185. CONFIG.PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ {10.000000} \
  186. CONFIG.PCW_ACT_PCAP_PERIPHERAL_FREQMHZ {200.000000} \
  187. CONFIG.PCW_ACT_QSPI_PERIPHERAL_FREQMHZ {200.000000} \
  188. CONFIG.PCW_ACT_SDIO_PERIPHERAL_FREQMHZ {10.000000} \
  189. CONFIG.PCW_ACT_SMC_PERIPHERAL_FREQMHZ {10.000000} \
  190. CONFIG.PCW_ACT_SPI_PERIPHERAL_FREQMHZ {10.000000} \
  191. CONFIG.PCW_ACT_TPIU_PERIPHERAL_FREQMHZ {200.000000} \
  192. CONFIG.PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ {111.111115} \
  193. CONFIG.PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ {111.111115} \
  194. CONFIG.PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ {111.111115} \
  195. CONFIG.PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ {111.111115} \
  196. CONFIG.PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ {111.111115} \
  197. CONFIG.PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ {111.111115} \
  198. CONFIG.PCW_ACT_UART_PERIPHERAL_FREQMHZ {100.000000} \
  199. CONFIG.PCW_ACT_WDT_PERIPHERAL_FREQMHZ {111.111115} \
  200. CONFIG.PCW_APU_CLK_RATIO_ENABLE {6:2:1} \
  201. CONFIG.PCW_APU_PERIPHERAL_FREQMHZ {667} \
  202. CONFIG.PCW_ARMPLL_CTRL_FBDIV {40} \
  203. CONFIG.PCW_CAN_PERIPHERAL_DIVISOR0 {1} \
  204. CONFIG.PCW_CAN_PERIPHERAL_DIVISOR1 {1} \
  205. CONFIG.PCW_CLK0_FREQ {50000000} \
  206. CONFIG.PCW_CLK1_FREQ {10000000} \
  207. CONFIG.PCW_CLK2_FREQ {10000000} \
  208. CONFIG.PCW_CLK3_FREQ {10000000} \
  209. CONFIG.PCW_CPU_CPU_6X4X_MAX_RANGE {667} \
  210. CONFIG.PCW_CPU_CPU_PLL_FREQMHZ {1333.333} \
  211. CONFIG.PCW_CPU_PERIPHERAL_CLKSRC {ARM PLL} \
  212. CONFIG.PCW_CPU_PERIPHERAL_DIVISOR0 {2} \
  213. CONFIG.PCW_CRYSTAL_PERIPHERAL_FREQMHZ {33.333333} \
  214. CONFIG.PCW_DCI_PERIPHERAL_CLKSRC {DDR PLL} \
  215. CONFIG.PCW_DCI_PERIPHERAL_DIVISOR0 {15} \
  216. CONFIG.PCW_DCI_PERIPHERAL_DIVISOR1 {7} \
  217. CONFIG.PCW_DCI_PERIPHERAL_FREQMHZ {10.159} \
  218. CONFIG.PCW_DDRPLL_CTRL_FBDIV {32} \
  219. CONFIG.PCW_DDR_DDR_PLL_FREQMHZ {1066.667} \
  220. CONFIG.PCW_DDR_HPRLPR_QUEUE_PARTITION {HPR/LPR} \
  221. CONFIG.PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL {15} \
  222. CONFIG.PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL {2} \
  223. CONFIG.PCW_DDR_PERIPHERAL_CLKSRC {DDR PLL} \
  224. CONFIG.PCW_DDR_PERIPHERAL_DIVISOR0 {2} \
  225. CONFIG.PCW_DDR_PORT0_HPR_ENABLE {0} \
  226. CONFIG.PCW_DDR_PORT1_HPR_ENABLE {0} \
  227. CONFIG.PCW_DDR_PORT2_HPR_ENABLE {0} \
  228. CONFIG.PCW_DDR_PORT3_HPR_ENABLE {0} \
  229. CONFIG.PCW_DDR_RAM_HIGHADDR {0x3FFFFFFF} \
  230. CONFIG.PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL {2} \
  231. CONFIG.PCW_ENET0_ENET0_IO {MIO 16 .. 27} \
  232. CONFIG.PCW_ENET0_GRP_MDIO_ENABLE {1} \
  233. CONFIG.PCW_ENET0_GRP_MDIO_IO {MIO 52 .. 53} \
  234. CONFIG.PCW_ENET0_PERIPHERAL_CLKSRC {IO PLL} \
  235. CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR0 {8} \
  236. CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR1 {1} \
  237. CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {1} \
  238. CONFIG.PCW_ENET0_PERIPHERAL_FREQMHZ {1000 Mbps} \
  239. CONFIG.PCW_ENET0_RESET_ENABLE {0} \
  240. CONFIG.PCW_ENET1_GRP_MDIO_ENABLE {0} \
  241. CONFIG.PCW_ENET1_PERIPHERAL_CLKSRC {IO PLL} \
  242. CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR0 {1} \
  243. CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR1 {1} \
  244. CONFIG.PCW_ENET1_PERIPHERAL_ENABLE {0} \
  245. CONFIG.PCW_ENET1_PERIPHERAL_FREQMHZ {1000 Mbps} \
  246. CONFIG.PCW_ENET1_RESET_ENABLE {0} \
  247. CONFIG.PCW_ENET_RESET_ENABLE {1} \
  248. CONFIG.PCW_ENET_RESET_POLARITY {Active Low} \
  249. CONFIG.PCW_ENET_RESET_SELECT {Share reset pin} \
  250. CONFIG.PCW_EN_4K_TIMER {0} \
  251. CONFIG.PCW_EN_EMIO_ENET0 {0} \
  252. CONFIG.PCW_EN_EMIO_GPIO {1} \
  253. CONFIG.PCW_EN_EMIO_I2C0 {0} \
  254. CONFIG.PCW_EN_EMIO_I2C1 {0} \
  255. CONFIG.PCW_EN_ENET0 {1} \
  256. CONFIG.PCW_EN_GPIO {1} \
  257. CONFIG.PCW_EN_I2C0 {1} \
  258. CONFIG.PCW_EN_I2C1 {1} \
  259. CONFIG.PCW_EN_QSPI {1} \
  260. CONFIG.PCW_EN_SDIO0 {0} \
  261. CONFIG.PCW_EN_UART1 {1} \
  262. CONFIG.PCW_EN_USB0 {0} \
  263. CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR0 {5} \
  264. CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR1 {4} \
  265. CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR0 {1} \
  266. CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR1 {1} \
  267. CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR0 {1} \
  268. CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR1 {1} \
  269. CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR0 {1} \
  270. CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR1 {1} \
  271. CONFIG.PCW_FPGA_FCLK0_ENABLE {1} \
  272. CONFIG.PCW_FPGA_FCLK1_ENABLE {0} \
  273. CONFIG.PCW_FPGA_FCLK2_ENABLE {0} \
  274. CONFIG.PCW_FPGA_FCLK3_ENABLE {0} \
  275. CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {1} \
  276. CONFIG.PCW_GPIO_EMIO_GPIO_IO {26} \
  277. CONFIG.PCW_GPIO_EMIO_GPIO_WIDTH {26} \
  278. CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1} \
  279. CONFIG.PCW_GPIO_MIO_GPIO_IO {MIO} \
  280. CONFIG.PCW_GPIO_PERIPHERAL_ENABLE {0} \
  281. CONFIG.PCW_I2C0_GRP_INT_ENABLE {1} \
  282. CONFIG.PCW_I2C0_GRP_INT_IO {EMIO} \
  283. CONFIG.PCW_I2C0_I2C0_IO {MIO 14 .. 15} \
  284. CONFIG.PCW_I2C0_PERIPHERAL_ENABLE {1} \
  285. CONFIG.PCW_I2C0_RESET_ENABLE {0} \
  286. CONFIG.PCW_I2C1_GRP_INT_ENABLE {1} \
  287. CONFIG.PCW_I2C1_GRP_INT_IO {EMIO} \
  288. CONFIG.PCW_I2C1_I2C1_IO {MIO 12 .. 13} \
  289. CONFIG.PCW_I2C1_PERIPHERAL_ENABLE {1} \
  290. CONFIG.PCW_I2C1_RESET_ENABLE {0} \
  291. CONFIG.PCW_I2C_PERIPHERAL_FREQMHZ {111.111115} \
  292. CONFIG.PCW_I2C_RESET_ENABLE {1} \
  293. CONFIG.PCW_I2C_RESET_SELECT {Share reset pin} \
  294. CONFIG.PCW_IOPLL_CTRL_FBDIV {30} \
  295. CONFIG.PCW_IO_IO_PLL_FREQMHZ {1000.000} \
  296. CONFIG.PCW_IRQ_F2P_MODE {DIRECT} \
  297. CONFIG.PCW_MIO_0_DIRECTION {inout} \
  298. CONFIG.PCW_MIO_0_IOTYPE {LVCMOS 3.3V} \
  299. CONFIG.PCW_MIO_0_PULLUP {enabled} \
  300. CONFIG.PCW_MIO_0_SLEW {slow} \
  301. CONFIG.PCW_MIO_10_DIRECTION {inout} \
  302. CONFIG.PCW_MIO_10_IOTYPE {LVCMOS 3.3V} \
  303. CONFIG.PCW_MIO_10_PULLUP {enabled} \
  304. CONFIG.PCW_MIO_10_SLEW {slow} \
  305. CONFIG.PCW_MIO_11_DIRECTION {inout} \
  306. CONFIG.PCW_MIO_11_IOTYPE {LVCMOS 3.3V} \
  307. CONFIG.PCW_MIO_11_PULLUP {enabled} \
  308. CONFIG.PCW_MIO_11_SLEW {slow} \
  309. CONFIG.PCW_MIO_12_DIRECTION {inout} \
  310. CONFIG.PCW_MIO_12_IOTYPE {LVCMOS 3.3V} \
  311. CONFIG.PCW_MIO_12_PULLUP {enabled} \
  312. CONFIG.PCW_MIO_12_SLEW {slow} \
  313. CONFIG.PCW_MIO_13_DIRECTION {inout} \
  314. CONFIG.PCW_MIO_13_IOTYPE {LVCMOS 3.3V} \
  315. CONFIG.PCW_MIO_13_PULLUP {enabled} \
  316. CONFIG.PCW_MIO_13_SLEW {slow} \
  317. CONFIG.PCW_MIO_14_DIRECTION {inout} \
  318. CONFIG.PCW_MIO_14_IOTYPE {LVCMOS 3.3V} \
  319. CONFIG.PCW_MIO_14_PULLUP {enabled} \
  320. CONFIG.PCW_MIO_14_SLEW {slow} \
  321. CONFIG.PCW_MIO_15_DIRECTION {inout} \
  322. CONFIG.PCW_MIO_15_IOTYPE {LVCMOS 3.3V} \
  323. CONFIG.PCW_MIO_15_PULLUP {enabled} \
  324. CONFIG.PCW_MIO_15_SLEW {slow} \
  325. CONFIG.PCW_MIO_16_DIRECTION {out} \
  326. CONFIG.PCW_MIO_16_IOTYPE {LVCMOS 1.8V} \
  327. CONFIG.PCW_MIO_16_PULLUP {enabled} \
  328. CONFIG.PCW_MIO_16_SLEW {fast} \
  329. CONFIG.PCW_MIO_17_DIRECTION {out} \
  330. CONFIG.PCW_MIO_17_IOTYPE {LVCMOS 1.8V} \
  331. CONFIG.PCW_MIO_17_PULLUP {enabled} \
  332. CONFIG.PCW_MIO_17_SLEW {fast} \
  333. CONFIG.PCW_MIO_18_DIRECTION {out} \
  334. CONFIG.PCW_MIO_18_IOTYPE {LVCMOS 1.8V} \
  335. CONFIG.PCW_MIO_18_PULLUP {enabled} \
  336. CONFIG.PCW_MIO_18_SLEW {fast} \
  337. CONFIG.PCW_MIO_19_DIRECTION {out} \
  338. CONFIG.PCW_MIO_19_IOTYPE {LVCMOS 1.8V} \
  339. CONFIG.PCW_MIO_19_PULLUP {enabled} \
  340. CONFIG.PCW_MIO_19_SLEW {fast} \
  341. CONFIG.PCW_MIO_1_DIRECTION {out} \
  342. CONFIG.PCW_MIO_1_IOTYPE {LVCMOS 3.3V} \
  343. CONFIG.PCW_MIO_1_PULLUP {enabled} \
  344. CONFIG.PCW_MIO_1_SLEW {slow} \
  345. CONFIG.PCW_MIO_20_DIRECTION {out} \
  346. CONFIG.PCW_MIO_20_IOTYPE {LVCMOS 1.8V} \
  347. CONFIG.PCW_MIO_20_PULLUP {enabled} \
  348. CONFIG.PCW_MIO_20_SLEW {fast} \
  349. CONFIG.PCW_MIO_21_DIRECTION {out} \
  350. CONFIG.PCW_MIO_21_IOTYPE {LVCMOS 1.8V} \
  351. CONFIG.PCW_MIO_21_PULLUP {enabled} \
  352. CONFIG.PCW_MIO_21_SLEW {fast} \
  353. CONFIG.PCW_MIO_22_DIRECTION {in} \
  354. CONFIG.PCW_MIO_22_IOTYPE {LVCMOS 1.8V} \
  355. CONFIG.PCW_MIO_22_PULLUP {enabled} \
  356. CONFIG.PCW_MIO_22_SLEW {fast} \
  357. CONFIG.PCW_MIO_23_DIRECTION {in} \
  358. CONFIG.PCW_MIO_23_IOTYPE {LVCMOS 1.8V} \
  359. CONFIG.PCW_MIO_23_PULLUP {enabled} \
  360. CONFIG.PCW_MIO_23_SLEW {fast} \
  361. CONFIG.PCW_MIO_24_DIRECTION {in} \
  362. CONFIG.PCW_MIO_24_IOTYPE {LVCMOS 1.8V} \
  363. CONFIG.PCW_MIO_24_PULLUP {enabled} \
  364. CONFIG.PCW_MIO_24_SLEW {fast} \
  365. CONFIG.PCW_MIO_25_DIRECTION {in} \
  366. CONFIG.PCW_MIO_25_IOTYPE {LVCMOS 1.8V} \
  367. CONFIG.PCW_MIO_25_PULLUP {enabled} \
  368. CONFIG.PCW_MIO_25_SLEW {fast} \
  369. CONFIG.PCW_MIO_26_DIRECTION {in} \
  370. CONFIG.PCW_MIO_26_IOTYPE {LVCMOS 1.8V} \
  371. CONFIG.PCW_MIO_26_PULLUP {enabled} \
  372. CONFIG.PCW_MIO_26_SLEW {fast} \
  373. CONFIG.PCW_MIO_27_DIRECTION {in} \
  374. CONFIG.PCW_MIO_27_IOTYPE {LVCMOS 1.8V} \
  375. CONFIG.PCW_MIO_27_PULLUP {enabled} \
  376. CONFIG.PCW_MIO_27_SLEW {fast} \
  377. CONFIG.PCW_MIO_28_DIRECTION {inout} \
  378. CONFIG.PCW_MIO_28_IOTYPE {LVCMOS 1.8V} \
  379. CONFIG.PCW_MIO_28_PULLUP {enabled} \
  380. CONFIG.PCW_MIO_28_SLEW {fast} \
  381. CONFIG.PCW_MIO_29_DIRECTION {inout} \
  382. CONFIG.PCW_MIO_29_IOTYPE {LVCMOS 1.8V} \
  383. CONFIG.PCW_MIO_29_PULLUP {enabled} \
  384. CONFIG.PCW_MIO_29_SLEW {fast} \
  385. CONFIG.PCW_MIO_2_DIRECTION {inout} \
  386. CONFIG.PCW_MIO_2_IOTYPE {LVCMOS 3.3V} \
  387. CONFIG.PCW_MIO_2_PULLUP {disabled} \
  388. CONFIG.PCW_MIO_2_SLEW {slow} \
  389. CONFIG.PCW_MIO_30_DIRECTION {inout} \
  390. CONFIG.PCW_MIO_30_IOTYPE {LVCMOS 1.8V} \
  391. CONFIG.PCW_MIO_30_PULLUP {enabled} \
  392. CONFIG.PCW_MIO_30_SLEW {fast} \
  393. CONFIG.PCW_MIO_31_DIRECTION {inout} \
  394. CONFIG.PCW_MIO_31_IOTYPE {LVCMOS 1.8V} \
  395. CONFIG.PCW_MIO_31_PULLUP {enabled} \
  396. CONFIG.PCW_MIO_31_SLEW {fast} \
  397. CONFIG.PCW_MIO_32_DIRECTION {inout} \
  398. CONFIG.PCW_MIO_32_IOTYPE {LVCMOS 1.8V} \
  399. CONFIG.PCW_MIO_32_PULLUP {enabled} \
  400. CONFIG.PCW_MIO_32_SLEW {fast} \
  401. CONFIG.PCW_MIO_33_DIRECTION {inout} \
  402. CONFIG.PCW_MIO_33_IOTYPE {LVCMOS 1.8V} \
  403. CONFIG.PCW_MIO_33_PULLUP {enabled} \
  404. CONFIG.PCW_MIO_33_SLEW {fast} \
  405. CONFIG.PCW_MIO_34_DIRECTION {inout} \
  406. CONFIG.PCW_MIO_34_IOTYPE {LVCMOS 1.8V} \
  407. CONFIG.PCW_MIO_34_PULLUP {enabled} \
  408. CONFIG.PCW_MIO_34_SLEW {fast} \
  409. CONFIG.PCW_MIO_35_DIRECTION {inout} \
  410. CONFIG.PCW_MIO_35_IOTYPE {LVCMOS 1.8V} \
  411. CONFIG.PCW_MIO_35_PULLUP {enabled} \
  412. CONFIG.PCW_MIO_35_SLEW {fast} \
  413. CONFIG.PCW_MIO_36_DIRECTION {inout} \
  414. CONFIG.PCW_MIO_36_IOTYPE {LVCMOS 1.8V} \
  415. CONFIG.PCW_MIO_36_PULLUP {enabled} \
  416. CONFIG.PCW_MIO_36_SLEW {fast} \
  417. CONFIG.PCW_MIO_37_DIRECTION {inout} \
  418. CONFIG.PCW_MIO_37_IOTYPE {LVCMOS 1.8V} \
  419. CONFIG.PCW_MIO_37_PULLUP {enabled} \
  420. CONFIG.PCW_MIO_37_SLEW {fast} \
  421. CONFIG.PCW_MIO_38_DIRECTION {inout} \
  422. CONFIG.PCW_MIO_38_IOTYPE {LVCMOS 1.8V} \
  423. CONFIG.PCW_MIO_38_PULLUP {enabled} \
  424. CONFIG.PCW_MIO_38_SLEW {fast} \
  425. CONFIG.PCW_MIO_39_DIRECTION {inout} \
  426. CONFIG.PCW_MIO_39_IOTYPE {LVCMOS 1.8V} \
  427. CONFIG.PCW_MIO_39_PULLUP {enabled} \
  428. CONFIG.PCW_MIO_39_SLEW {fast} \
  429. CONFIG.PCW_MIO_3_DIRECTION {inout} \
  430. CONFIG.PCW_MIO_3_IOTYPE {LVCMOS 3.3V} \
  431. CONFIG.PCW_MIO_3_PULLUP {disabled} \
  432. CONFIG.PCW_MIO_3_SLEW {slow} \
  433. CONFIG.PCW_MIO_40_DIRECTION {inout} \
  434. CONFIG.PCW_MIO_40_IOTYPE {LVCMOS 1.8V} \
  435. CONFIG.PCW_MIO_40_PULLUP {enabled} \
  436. CONFIG.PCW_MIO_40_SLEW {slow} \
  437. CONFIG.PCW_MIO_41_DIRECTION {inout} \
  438. CONFIG.PCW_MIO_41_IOTYPE {LVCMOS 1.8V} \
  439. CONFIG.PCW_MIO_41_PULLUP {enabled} \
  440. CONFIG.PCW_MIO_41_SLEW {slow} \
  441. CONFIG.PCW_MIO_42_DIRECTION {inout} \
  442. CONFIG.PCW_MIO_42_IOTYPE {LVCMOS 1.8V} \
  443. CONFIG.PCW_MIO_42_PULLUP {enabled} \
  444. CONFIG.PCW_MIO_42_SLEW {slow} \
  445. CONFIG.PCW_MIO_43_DIRECTION {inout} \
  446. CONFIG.PCW_MIO_43_IOTYPE {LVCMOS 1.8V} \
  447. CONFIG.PCW_MIO_43_PULLUP {enabled} \
  448. CONFIG.PCW_MIO_43_SLEW {slow} \
  449. CONFIG.PCW_MIO_44_DIRECTION {inout} \
  450. CONFIG.PCW_MIO_44_IOTYPE {LVCMOS 1.8V} \
  451. CONFIG.PCW_MIO_44_PULLUP {enabled} \
  452. CONFIG.PCW_MIO_44_SLEW {slow} \
  453. CONFIG.PCW_MIO_45_DIRECTION {inout} \
  454. CONFIG.PCW_MIO_45_IOTYPE {LVCMOS 1.8V} \
  455. CONFIG.PCW_MIO_45_PULLUP {enabled} \
  456. CONFIG.PCW_MIO_45_SLEW {slow} \
  457. CONFIG.PCW_MIO_46_DIRECTION {out} \
  458. CONFIG.PCW_MIO_46_IOTYPE {LVCMOS 1.8V} \
  459. CONFIG.PCW_MIO_46_PULLUP {enabled} \
  460. CONFIG.PCW_MIO_46_SLEW {slow} \
  461. CONFIG.PCW_MIO_47_DIRECTION {in} \
  462. CONFIG.PCW_MIO_47_IOTYPE {LVCMOS 1.8V} \
  463. CONFIG.PCW_MIO_47_PULLUP {enabled} \
  464. CONFIG.PCW_MIO_47_SLEW {slow} \
  465. CONFIG.PCW_MIO_48_DIRECTION {out} \
  466. CONFIG.PCW_MIO_48_IOTYPE {LVCMOS 1.8V} \
  467. CONFIG.PCW_MIO_48_PULLUP {enabled} \
  468. CONFIG.PCW_MIO_48_SLEW {slow} \
  469. CONFIG.PCW_MIO_49_DIRECTION {in} \
  470. CONFIG.PCW_MIO_49_IOTYPE {LVCMOS 1.8V} \
  471. CONFIG.PCW_MIO_49_PULLUP {enabled} \
  472. CONFIG.PCW_MIO_49_SLEW {slow} \
  473. CONFIG.PCW_MIO_4_DIRECTION {inout} \
  474. CONFIG.PCW_MIO_4_IOTYPE {LVCMOS 3.3V} \
  475. CONFIG.PCW_MIO_4_PULLUP {disabled} \
  476. CONFIG.PCW_MIO_4_SLEW {slow} \
  477. CONFIG.PCW_MIO_50_DIRECTION {inout} \
  478. CONFIG.PCW_MIO_50_IOTYPE {LVCMOS 1.8V} \
  479. CONFIG.PCW_MIO_50_PULLUP {enabled} \
  480. CONFIG.PCW_MIO_50_SLEW {slow} \
  481. CONFIG.PCW_MIO_51_DIRECTION {inout} \
  482. CONFIG.PCW_MIO_51_IOTYPE {LVCMOS 1.8V} \
  483. CONFIG.PCW_MIO_51_PULLUP {enabled} \
  484. CONFIG.PCW_MIO_51_SLEW {slow} \
  485. CONFIG.PCW_MIO_52_DIRECTION {out} \
  486. CONFIG.PCW_MIO_52_IOTYPE {LVCMOS 1.8V} \
  487. CONFIG.PCW_MIO_52_PULLUP {enabled} \
  488. CONFIG.PCW_MIO_52_SLEW {slow} \
  489. CONFIG.PCW_MIO_53_DIRECTION {inout} \
  490. CONFIG.PCW_MIO_53_IOTYPE {LVCMOS 1.8V} \
  491. CONFIG.PCW_MIO_53_PULLUP {enabled} \
  492. CONFIG.PCW_MIO_53_SLEW {slow} \
  493. CONFIG.PCW_MIO_5_DIRECTION {inout} \
  494. CONFIG.PCW_MIO_5_IOTYPE {LVCMOS 3.3V} \
  495. CONFIG.PCW_MIO_5_PULLUP {disabled} \
  496. CONFIG.PCW_MIO_5_SLEW {slow} \
  497. CONFIG.PCW_MIO_6_DIRECTION {out} \
  498. CONFIG.PCW_MIO_6_IOTYPE {LVCMOS 3.3V} \
  499. CONFIG.PCW_MIO_6_PULLUP {disabled} \
  500. CONFIG.PCW_MIO_6_SLEW {slow} \
  501. CONFIG.PCW_MIO_7_DIRECTION {out} \
  502. CONFIG.PCW_MIO_7_IOTYPE {LVCMOS 3.3V} \
  503. CONFIG.PCW_MIO_7_PULLUP {disabled} \
  504. CONFIG.PCW_MIO_7_SLEW {slow} \
  505. CONFIG.PCW_MIO_8_DIRECTION {out} \
  506. CONFIG.PCW_MIO_8_IOTYPE {LVCMOS 3.3V} \
  507. CONFIG.PCW_MIO_8_PULLUP {disabled} \
  508. CONFIG.PCW_MIO_8_SLEW {slow} \
  509. CONFIG.PCW_MIO_9_DIRECTION {inout} \
  510. CONFIG.PCW_MIO_9_IOTYPE {LVCMOS 3.3V} \
  511. CONFIG.PCW_MIO_9_PULLUP {enabled} \
  512. CONFIG.PCW_MIO_9_SLEW {slow} \
  513. CONFIG.PCW_MIO_TREE_PERIPHERALS {GPIO#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#GPIO#Quad SPI Flash#GPIO#GPIO#GPIO#I2C 1#I2C 1#I2C 0#I2C 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#UART 1#UART 1#GPIO#GPIO#Enet 0#Enet 0} \
  514. CONFIG.PCW_MIO_TREE_SIGNALS {gpio0#qspi0_ss_b#qspi0_io0#qspi0_io1#qspi0_io2#qspi0_io3/HOLD_B#qspi0_sclk#gpio7#qspi_fbclk#gpio9#gpio10#gpio11#scl#sda#scl#sda#tx_clk#txd0#txd1#txd2#txd3#tx_ctl#rx_clk#rxd0#rxd1#rxd2#rxd3#rx_ctl#gpio28#gpio29#gpio30#gpio31#gpio32#gpio33#gpio34#gpio35#gpio36#gpio37#gpio38#gpio39#gpio40#gpio41#gpio42#gpio43#gpio44#gpio45#gpio46#gpio47#tx#rx#gpio50#gpio51#mdc#mdio} \
  515. CONFIG.PCW_NAND_GRP_D8_ENABLE {0} \
  516. CONFIG.PCW_NAND_PERIPHERAL_ENABLE {0} \
  517. CONFIG.PCW_NOR_GRP_A25_ENABLE {0} \
  518. CONFIG.PCW_NOR_GRP_CS0_ENABLE {0} \
  519. CONFIG.PCW_NOR_GRP_CS1_ENABLE {0} \
  520. CONFIG.PCW_NOR_GRP_SRAM_CS0_ENABLE {0} \
  521. CONFIG.PCW_NOR_GRP_SRAM_CS1_ENABLE {0} \
  522. CONFIG.PCW_NOR_GRP_SRAM_INT_ENABLE {0} \
  523. CONFIG.PCW_NOR_PERIPHERAL_ENABLE {0} \
  524. CONFIG.PCW_OVERRIDE_BASIC_CLOCK {0} \
  525. CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY0 {0.221} \
  526. CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY1 {0.222} \
  527. CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY2 {0.217} \
  528. CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY3 {0.244} \
  529. CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_0 {-0.050} \
  530. CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_1 {-0.044} \
  531. CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_2 {-0.035} \
  532. CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_3 {-0.100} \
  533. CONFIG.PCW_PCAP_PERIPHERAL_CLKSRC {IO PLL} \
  534. CONFIG.PCW_PCAP_PERIPHERAL_DIVISOR0 {5} \
  535. CONFIG.PCW_PCAP_PERIPHERAL_FREQMHZ {200} \
  536. CONFIG.PCW_PJTAG_PERIPHERAL_ENABLE {0} \
  537. CONFIG.PCW_PLL_BYPASSMODE_ENABLE {0} \
  538. CONFIG.PCW_PRESET_BANK0_VOLTAGE {LVCMOS 3.3V} \
  539. CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 1.8V} \
  540. CONFIG.PCW_QSPI_GRP_FBCLK_ENABLE {1} \
  541. CONFIG.PCW_QSPI_GRP_FBCLK_IO {MIO 8} \
  542. CONFIG.PCW_QSPI_GRP_IO1_ENABLE {0} \
  543. CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE {1} \
  544. CONFIG.PCW_QSPI_GRP_SINGLE_SS_IO {MIO 1 .. 6} \
  545. CONFIG.PCW_QSPI_GRP_SS1_ENABLE {0} \
  546. CONFIG.PCW_QSPI_INTERNAL_HIGHADDRESS {0xFCFFFFFF} \
  547. CONFIG.PCW_QSPI_PERIPHERAL_CLKSRC {IO PLL} \
  548. CONFIG.PCW_QSPI_PERIPHERAL_DIVISOR0 {5} \
  549. CONFIG.PCW_QSPI_PERIPHERAL_ENABLE {1} \
  550. CONFIG.PCW_QSPI_PERIPHERAL_FREQMHZ {200} \
  551. CONFIG.PCW_QSPI_QSPI_IO {MIO 1 .. 6} \
  552. CONFIG.PCW_SD0_GRP_CD_ENABLE {0} \
  553. CONFIG.PCW_SD0_GRP_CD_IO {<Select>} \
  554. CONFIG.PCW_SD0_GRP_POW_ENABLE {0} \
  555. CONFIG.PCW_SD0_GRP_WP_ENABLE {0} \
  556. CONFIG.PCW_SD0_PERIPHERAL_ENABLE {0} \
  557. CONFIG.PCW_SD0_SD0_IO {<Select>} \
  558. CONFIG.PCW_SDIO_PERIPHERAL_CLKSRC {IO PLL} \
  559. CONFIG.PCW_SDIO_PERIPHERAL_DIVISOR0 {1} \
  560. CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ {50} \
  561. CONFIG.PCW_SDIO_PERIPHERAL_VALID {0} \
  562. CONFIG.PCW_SINGLE_QSPI_DATA_MODE {x4} \
  563. CONFIG.PCW_SMC_PERIPHERAL_CLKSRC {IO PLL} \
  564. CONFIG.PCW_SMC_PERIPHERAL_DIVISOR0 {1} \
  565. CONFIG.PCW_SMC_PERIPHERAL_FREQMHZ {100} \
  566. CONFIG.PCW_SPI_PERIPHERAL_DIVISOR0 {1} \
  567. CONFIG.PCW_TPIU_PERIPHERAL_CLKSRC {External} \
  568. CONFIG.PCW_TPIU_PERIPHERAL_DIVISOR0 {1} \
  569. CONFIG.PCW_TPIU_PERIPHERAL_FREQMHZ {200} \
  570. CONFIG.PCW_UART1_BAUD_RATE {115200} \
  571. CONFIG.PCW_UART1_GRP_FULL_ENABLE {0} \
  572. CONFIG.PCW_UART1_PERIPHERAL_ENABLE {1} \
  573. CONFIG.PCW_UART1_UART1_IO {MIO 48 .. 49} \
  574. CONFIG.PCW_UART_PERIPHERAL_CLKSRC {IO PLL} \
  575. CONFIG.PCW_UART_PERIPHERAL_DIVISOR0 {10} \
  576. CONFIG.PCW_UART_PERIPHERAL_FREQMHZ {100} \
  577. CONFIG.PCW_UART_PERIPHERAL_VALID {1} \
  578. CONFIG.PCW_UIPARAM_ACT_DDR_FREQ_MHZ {533.333374} \
  579. CONFIG.PCW_UIPARAM_DDR_ADV_ENABLE {0} \
  580. CONFIG.PCW_UIPARAM_DDR_AL {0} \
  581. CONFIG.PCW_UIPARAM_DDR_BANK_ADDR_COUNT {3} \
  582. CONFIG.PCW_UIPARAM_DDR_BL {8} \
  583. CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0 {0.221} \
  584. CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1 {0.222} \
  585. CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2 {0.217} \
  586. CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3 {0.244} \
  587. CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH {32 Bit} \
  588. CONFIG.PCW_UIPARAM_DDR_CL {7} \
  589. CONFIG.PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM {18.8} \
  590. CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH {80.4535} \
  591. CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY {160} \
  592. CONFIG.PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM {18.8} \
  593. CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH {80.4535} \
  594. CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY {160} \
  595. CONFIG.PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM {18.8} \
  596. CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH {80.4535} \
  597. CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY {160} \
  598. CONFIG.PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM {18.8} \
  599. CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH {80.4535} \
  600. CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY {160} \
  601. CONFIG.PCW_UIPARAM_DDR_CLOCK_STOP_EN {0} \
  602. CONFIG.PCW_UIPARAM_DDR_COL_ADDR_COUNT {10} \
  603. CONFIG.PCW_UIPARAM_DDR_CWL {6} \
  604. CONFIG.PCW_UIPARAM_DDR_DEVICE_CAPACITY {4096 MBits} \
  605. CONFIG.PCW_UIPARAM_DDR_DQS_0_LENGTH_MM {22.8} \
  606. CONFIG.PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH {105.056} \
  607. CONFIG.PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY {160} \
  608. CONFIG.PCW_UIPARAM_DDR_DQS_1_LENGTH_MM {27.9} \
  609. CONFIG.PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH {66.904} \
  610. CONFIG.PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY {160} \
  611. CONFIG.PCW_UIPARAM_DDR_DQS_2_LENGTH_MM {22.9} \
  612. CONFIG.PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH {89.1715} \
  613. CONFIG.PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY {160} \
  614. CONFIG.PCW_UIPARAM_DDR_DQS_3_LENGTH_MM {29.4} \
  615. CONFIG.PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH {113.63} \
  616. CONFIG.PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY {160} \
  617. CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 {-0.050} \
  618. CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 {-0.044} \
  619. CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 {-0.035} \
  620. CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 {-0.100} \
  621. CONFIG.PCW_UIPARAM_DDR_DQ_0_LENGTH_MM {22.8} \
  622. CONFIG.PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH {98.503} \
  623. CONFIG.PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY {160} \
  624. CONFIG.PCW_UIPARAM_DDR_DQ_1_LENGTH_MM {27.9} \
  625. CONFIG.PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH {68.5855} \
  626. CONFIG.PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY {160} \
  627. CONFIG.PCW_UIPARAM_DDR_DQ_2_LENGTH_MM {22.9} \
  628. CONFIG.PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH {90.295} \
  629. CONFIG.PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY {160} \
  630. CONFIG.PCW_UIPARAM_DDR_DQ_3_LENGTH_MM {29.4} \
  631. CONFIG.PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH {103.977} \
  632. CONFIG.PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY {160} \
  633. CONFIG.PCW_UIPARAM_DDR_DRAM_WIDTH {16 Bits} \
  634. CONFIG.PCW_UIPARAM_DDR_ECC {Disabled} \
  635. CONFIG.PCW_UIPARAM_DDR_ENABLE {1} \
  636. CONFIG.PCW_UIPARAM_DDR_FREQ_MHZ {533.333333} \
  637. CONFIG.PCW_UIPARAM_DDR_HIGH_TEMP {Normal (0-85)} \
  638. CONFIG.PCW_UIPARAM_DDR_MEMORY_TYPE {DDR 3 (Low Voltage)} \
  639. CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41K256M16 RE-125} \
  640. CONFIG.PCW_UIPARAM_DDR_ROW_ADDR_COUNT {15} \
  641. CONFIG.PCW_UIPARAM_DDR_SPEED_BIN {DDR3_1066F} \
  642. CONFIG.PCW_UIPARAM_DDR_TRAIN_DATA_EYE {1} \
  643. CONFIG.PCW_UIPARAM_DDR_TRAIN_READ_GATE {1} \
  644. CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL {1} \
  645. CONFIG.PCW_UIPARAM_DDR_T_FAW {40.0} \
  646. CONFIG.PCW_UIPARAM_DDR_T_RAS_MIN {35.0} \
  647. CONFIG.PCW_UIPARAM_DDR_T_RC {48.75} \
  648. CONFIG.PCW_UIPARAM_DDR_T_RCD {7} \
  649. CONFIG.PCW_UIPARAM_DDR_T_RP {7} \
  650. CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF {0} \
  651. CONFIG.PCW_USB0_PERIPHERAL_ENABLE {0} \
  652. CONFIG.PCW_USB0_PERIPHERAL_FREQMHZ {60} \
  653. CONFIG.PCW_USB0_RESET_ENABLE {1} \
  654. CONFIG.PCW_USB0_RESET_IO {MIO 46} \
  655. CONFIG.PCW_USB0_USB0_IO {<Select>} \
  656. CONFIG.PCW_USB1_RESET_ENABLE {0} \
  657. CONFIG.PCW_USB_RESET_ENABLE {1} \
  658. CONFIG.PCW_USB_RESET_POLARITY {Active Low} \
  659. CONFIG.PCW_USB_RESET_SELECT {<Select>} \
  660. CONFIG.PCW_USE_AXI_NONSECURE {0} \
  661. CONFIG.PCW_USE_CROSS_TRIGGER {0} \
  662. CONFIG.PCW_USE_M_AXI_GP0 {0} \
  663. ] $processing_system7_0
  664. # Create interface connections
  665. connect_bd_intf_net -intf_net processing_system7_0_DDR [get_bd_intf_ports DDR] [get_bd_intf_pins processing_system7_0/DDR]
  666. connect_bd_intf_net -intf_net processing_system7_0_FIXED_IO [get_bd_intf_ports FIXED_IO] [get_bd_intf_pins processing_system7_0/FIXED_IO]
  667. connect_bd_intf_net -intf_net processing_system7_0_GPIO_0 [get_bd_intf_ports GPIO_0_0] [get_bd_intf_pins processing_system7_0/GPIO_0]
  668. # Create port connections
  669. # Create address segments
  670. # Perform GUI Layout
  671. regenerate_bd_layout -layout_string {
  672. "ActiveEmotionalView":"Default View",
  673. "Default View_ScaleFactor":"1.0",
  674. "Default View_TopLeft":"-337,-352",
  675. "ExpandedHierarchyInLayout":"",
  676. "guistr":"# # String gsaved with Nlview 7.0r6 2020-01-29 bk=1.5227 VDI=41 GEI=36 GUI=JA:10.0 non-TLS
  677. # -string -flagsOSRD
  678. preplace port DDR -pg 1 -lvl 2 -x 430 -y -120 -defaultsOSRD
  679. preplace port FIXED_IO -pg 1 -lvl 2 -x 430 -y -100 -defaultsOSRD
  680. preplace port GPIO_0_0 -pg 1 -lvl 2 -x 430 -y -140 -defaultsOSRD
  681. preplace inst processing_system7_0 -pg 1 -lvl 1 -x 210 -y -100 -defaultsOSRD
  682. preplace netloc processing_system7_0_GPIO_0 1 1 1 N -140
  683. preplace netloc processing_system7_0_FIXED_IO 1 1 1 NJ -100
  684. preplace netloc processing_system7_0_DDR 1 1 1 NJ -120
  685. levelinfo -pg 1 0 210 430
  686. pagesize -pg 1 -db -bbox -sgen 0 -220 550 200
  687. "
  688. }
  689. # Restore current instance
  690. current_bd_instance $oldCurInst
  691. validate_bd_design
  692. save_bd_design
  693. close_bd_design $design_name
  694. }
  695. cr_bd_design_1 ""
    INFO: [BD::TCL 103-2010] Currently there is no design <design_1> in project, so creating one...
    Wrote : <C:\AimaginProjects\Zybo\Hardware_Z7000\i2c_demo\project_1\project_1.srcs\sources_1\bd\design_1\design_1.bd>
    create_bd_design: Time (s): cpu = 00:00:04 ; elapsed = 00:00:07 . Memory (MB): peak = 1119.531 ; gain = 0.000
    INFO: [BD::TCL 103-2011] Checking if the following IPs exist in the project's IP catalog:
    xilinx.com:ip:processing_system7:5.5 .
    CRITICAL WARNING: [PSU-1] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.050 . PS DDR interfaces might fail when entering negative DQS skew values.
    CRITICAL WARNING: [PSU-2] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.044 . PS DDR interfaces might fail when entering negative DQS skew values.
    CRITICAL WARNING: [PSU-3] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 has negative value -0.035 . PS DDR interfaces might fail when entering negative DQS skew values.
    CRITICAL WARNING: [PSU-4] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 has negative value -0.100 . PS DDR interfaces might fail when entering negative DQS skew values.
    CRITICAL WARNING: [PSU-1] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.050 . PS DDR interfaces might fail when entering negative DQS skew values.
    CRITICAL WARNING: [PSU-2] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.044 . PS DDR interfaces might fail when entering negative DQS skew values.
    CRITICAL WARNING: [PSU-3] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 has negative value -0.035 . PS DDR interfaces might fail when entering negative DQS skew values.
    CRITICAL WARNING: [PSU-4] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 has negative value -0.100 . PS DDR interfaces might fail when entering negative DQS skew values.
    Wrote : <C:\AimaginProjects\Zybo\Hardware_Z7000\i2c_demo\project_1\project_1.srcs\sources_1\bd\design_1\design_1.bd>
    Wrote : <C:/AimaginProjects/Zybo/Hardware_Z7000/i2c_demo/project_1/project_1.srcs/sources_1/bd/design_1/ui/bd_1f5defd0.ui>
  696. set_property REGISTERED_WITH_MANAGER "1" [get_files design_1.bd ]
  697. set_property SYNTH_CHECKPOINT_MODE "Hierarchical" [get_files design_1.bd ]
  698. if { [get_property IS_LOCKED [ get_files -norecurse design_1.bd] ] == 1 } {
  699. import_files -fileset sources_1 [file normalize "${origin_dir}/project_1/project_1.gen/sources_1/bd/design_1/hdl/design_1_wrapper.vhd" ]
  700. } else {
  701. set wrapper_path [make_wrapper -fileset sources_1 -files [ get_files -norecurse design_1.bd] -top]
  702. add_files -norecurse -fileset sources_1 $wrapper_path
  703. }
    INFO: [BD 41-1662] The design 'design_1.bd' is already validated. Therefore parameter propagation will not be re-run.
    VHDL Output written to : c:/AimaginProjects/Zybo/Hardware_Z7000/i2c_demo/project_1/project_1.gen/sources_1/bd/design_1/synth/design_1.vhd
    VHDL Output written to : c:/AimaginProjects/Zybo/Hardware_Z7000/i2c_demo/project_1/project_1.gen/sources_1/bd/design_1/sim/design_1.vhd
    VHDL Output written to : c:/AimaginProjects/Zybo/Hardware_Z7000/i2c_demo/project_1/project_1.gen/sources_1/bd/design_1/hdl/design_1_wrapper.vhd
    make_wrapper: Time (s): cpu = 00:00:01 ; elapsed = 00:00:07 . Memory (MB): peak = 1420.555 ; gain = 126.723
  704. if {[string equal [get_runs -quiet synth_1] ""]} {
  705. create_run -name synth_1 -part xc7z020clg400-1 -flow {Vivado Synthesis 2020} -strategy "Vivado Synthesis Defaults" -report_strategy {No Reports} -constrset constrs_1
  706. } else {
  707. set_property strategy "Vivado Synthesis Defaults" [get_runs synth_1]
  708. set_property flow "Vivado Synthesis 2020" [get_runs synth_1]
  709. }
  710. set obj [get_runs synth_1]
  711. set_property set_report_strategy_name 1 $obj
  712. set_property report_strategy {Vivado Synthesis Default Reports} $obj
  713. set_property set_report_strategy_name 0 $obj
  714. if { [ string equal [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0] "" ] } {
  715. create_report_config -report_name synth_1_synth_report_utilization_0 -report_type report_utilization:1.0 -steps synth_design -runs synth_1
  716. }
  717. set obj [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0]
  718. if { $obj != "" } {
  719. }
  720. set obj [get_runs synth_1]
  721. set_property -name "strategy" -value "Vivado Synthesis Defaults" -objects $obj
  722. current_run -synthesis [get_runs synth_1]
  723. if {[string equal [get_runs -quiet impl_1] ""]} {
  724. create_run -name impl_1 -part xc7z020clg400-1 -flow {Vivado Implementation 2020} -strategy "Vivado Implementation Defaults" -report_strategy {No Reports} -constrset constrs_1 -parent_run synth_1
  725. } else {
  726. set_property strategy "Vivado Implementation Defaults" [get_runs impl_1]
  727. set_property flow "Vivado Implementation 2020" [get_runs impl_1]
  728. }
  729. set obj [get_runs impl_1]
  730. set_property set_report_strategy_name 1 $obj
  731. set_property report_strategy {Vivado Implementation Default Reports} $obj
  732. set_property set_report_strategy_name 0 $obj
  733. if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0] "" ] } {
  734. create_report_config -report_name impl_1_init_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps init_design -runs impl_1
  735. }
  736. set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0]
  737. if { $obj != "" } {
  738. set_property -name "is_enabled" -value "0" -objects $obj
  739. set_property -name "options.max_paths" -value "10" -objects $obj
  740. }
  741. if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0] "" ] } {
  742. create_report_config -report_name impl_1_opt_report_drc_0 -report_type report_drc:1.0 -steps opt_design -runs impl_1
  743. }
  744. set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0]
  745. if { $obj != "" } {
  746. }
  747. if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0] "" ] } {
  748. create_report_config -report_name impl_1_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps opt_design -runs impl_1
  749. }
  750. set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0]
  751. if { $obj != "" } {
  752. set_property -name "is_enabled" -value "0" -objects $obj
  753. set_property -name "options.max_paths" -value "10" -objects $obj
  754. }
  755. if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0] "" ] } {
  756. create_report_config -report_name impl_1_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps power_opt_design -runs impl_1
  757. }
  758. set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0]
  759. if { $obj != "" } {
  760. set_property -name "is_enabled" -value "0" -objects $obj
  761. set_property -name "options.max_paths" -value "10" -objects $obj
  762. }
  763. if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0] "" ] } {
  764. create_report_config -report_name impl_1_place_report_io_0 -report_type report_io:1.0 -steps place_design -runs impl_1
  765. }
  766. set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0]
  767. if { $obj != "" } {
  768. }
  769. if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0] "" ] } {
  770. create_report_config -report_name impl_1_place_report_utilization_0 -report_type report_utilization:1.0 -steps place_design -runs impl_1
  771. }
  772. set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0]
  773. if { $obj != "" } {
  774. }
  775. if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0] "" ] } {
  776. create_report_config -report_name impl_1_place_report_control_sets_0 -report_type report_control_sets:1.0 -steps place_design -runs impl_1
  777. }
  778. set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0]
  779. if { $obj != "" } {
  780. set_property -name "options.verbose" -value "1" -objects $obj
  781. }
  782. if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0] "" ] } {
  783. create_report_config -report_name impl_1_place_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1
  784. }
  785. set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0]
  786. if { $obj != "" } {
  787. set_property -name "is_enabled" -value "0" -objects $obj
  788. }
  789. if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1] "" ] } {
  790. create_report_config -report_name impl_1_place_report_incremental_reuse_1 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1
  791. }
  792. set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1]
  793. if { $obj != "" } {
  794. set_property -name "is_enabled" -value "0" -objects $obj
  795. }
  796. if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0] "" ] } {
  797. create_report_config -report_name impl_1_place_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps place_design -runs impl_1
  798. }
  799. set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0]
  800. if { $obj != "" } {
  801. set_property -name "is_enabled" -value "0" -objects $obj
  802. set_property -name "options.max_paths" -value "10" -objects $obj
  803. }
  804. if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0] "" ] } {
  805. create_report_config -report_name impl_1_post_place_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_place_power_opt_design -runs impl_1
  806. }
  807. set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0]
  808. if { $obj != "" } {
  809. set_property -name "is_enabled" -value "0" -objects $obj
  810. set_property -name "options.max_paths" -value "10" -objects $obj
  811. }
  812. if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0] "" ] } {
  813. create_report_config -report_name impl_1_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps phys_opt_design -runs impl_1
  814. }
  815. set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0]
  816. if { $obj != "" } {
  817. set_property -name "is_enabled" -value "0" -objects $obj
  818. set_property -name "options.max_paths" -value "10" -objects $obj
  819. }
  820. if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0] "" ] } {
  821. create_report_config -report_name impl_1_route_report_drc_0 -report_type report_drc:1.0 -steps route_design -runs impl_1
  822. }
  823. set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0]
  824. if { $obj != "" } {
  825. }
  826. if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0] "" ] } {
  827. create_report_config -report_name impl_1_route_report_methodology_0 -report_type report_methodology:1.0 -steps route_design -runs impl_1
  828. }
  829. set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0]
  830. if { $obj != "" } {
  831. }
  832. if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0] "" ] } {
  833. create_report_config -report_name impl_1_route_report_power_0 -report_type report_power:1.0 -steps route_design -runs impl_1
  834. }
  835. set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0]
  836. if { $obj != "" } {
  837. }
  838. if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0] "" ] } {
  839. create_report_config -report_name impl_1_route_report_route_status_0 -report_type report_route_status:1.0 -steps route_design -runs impl_1
  840. }
  841. set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0]
  842. if { $obj != "" } {
  843. }
  844. if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0] "" ] } {
  845. create_report_config -report_name impl_1_route_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps route_design -runs impl_1
  846. }
  847. set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0]
  848. if { $obj != "" } {
  849. set_property -name "options.max_paths" -value "10" -objects $obj
  850. }
  851. if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0] "" ] } {
  852. create_report_config -report_name impl_1_route_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps route_design -runs impl_1
  853. }
  854. set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0]
  855. if { $obj != "" } {
  856. }
  857. if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0] "" ] } {
  858. create_report_config -report_name impl_1_route_report_clock_utilization_0 -report_type report_clock_utilization:1.0 -steps route_design -runs impl_1
  859. }
  860. set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0]
  861. if { $obj != "" } {
  862. }
  863. if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0] "" ] } {
  864. create_report_config -report_name impl_1_route_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps route_design -runs impl_1
  865. }
  866. set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0]
  867. if { $obj != "" } {
  868. set_property -name "options.warn_on_violation" -value "1" -objects $obj
  869. }
  870. if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0] "" ] } {
  871. create_report_config -report_name impl_1_post_route_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_route_phys_opt_design -runs impl_1
  872. }
  873. set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0]
  874. if { $obj != "" } {
  875. set_property -name "options.max_paths" -value "10" -objects $obj
  876. set_property -name "options.warn_on_violation" -value "1" -objects $obj
  877. }
  878. if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0] "" ] } {
  879. create_report_config -report_name impl_1_post_route_phys_opt_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps post_route_phys_opt_design -runs impl_1
  880. }
  881. set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0]
  882. if { $obj != "" } {
  883. set_property -name "options.warn_on_violation" -value "1" -objects $obj
  884. }
  885. set obj [get_runs impl_1]
  886. set_property -name "strategy" -value "Vivado Implementation Defaults" -objects $obj
  887. set_property -name "steps.write_bitstream.args.readback_file" -value "0" -objects $obj
  888. set_property -name "steps.write_bitstream.args.verbose" -value "0" -objects $obj
  889. current_run -implementation [get_runs impl_1]
  890. puts "INFO: Project created:${_xil_proj_name_}"
    INFO: Project created:project_1
  891. if {[string equal [get_dashboard_gadgets [ list "drc_1" ] ] ""]} {
  892. create_dashboard_gadget -name {drc_1} -type drc
  893. }
  894. set obj [get_dashboard_gadgets [ list "drc_1" ] ]
  895. set_property -name "reports" -value "impl_1#impl_1_route_report_drc_0" -objects $obj
  896. if {[string equal [get_dashboard_gadgets [ list "methodology_1" ] ] ""]} {
  897. create_dashboard_gadget -name {methodology_1} -type methodology
  898. }
  899. set obj [get_dashboard_gadgets [ list "methodology_1" ] ]
  900. set_property -name "reports" -value "impl_1#impl_1_route_report_methodology_0" -objects $obj
  901. if {[string equal [get_dashboard_gadgets [ list "power_1" ] ] ""]} {
  902. create_dashboard_gadget -name {power_1} -type power
  903. }
  904. set obj [get_dashboard_gadgets [ list "power_1" ] ]
  905. set_property -name "reports" -value "impl_1#impl_1_route_report_power_0" -objects $obj
  906. if {[string equal [get_dashboard_gadgets [ list "timing_1" ] ] ""]} {
  907. create_dashboard_gadget -name {timing_1} -type timing
  908. }
  909. set obj [get_dashboard_gadgets [ list "timing_1" ] ]
  910. set_property -name "reports" -value "impl_1#impl_1_route_report_timing_summary_0" -objects $obj
  911. if {[string equal [get_dashboard_gadgets [ list "utilization_1" ] ] ""]} {
  912. create_dashboard_gadget -name {utilization_1} -type utilization
  913. }
  914. set obj [get_dashboard_gadgets [ list "utilization_1" ] ]
  915. set_property -name "reports" -value "synth_1#synth_1_synth_report_utilization_0" -objects $obj
  916. set_property -name "run.step" -value "synth_design" -objects $obj
  917. set_property -name "run.type" -value "synthesis" -objects $obj
  918. if {[string equal [get_dashboard_gadgets [ list "utilization_2" ] ] ""]} {
  919. create_dashboard_gadget -name {utilization_2} -type utilization
  920. }
  921. set obj [get_dashboard_gadgets [ list "utilization_2" ] ]
  922. set_property -name "reports" -value "impl_1#impl_1_place_report_utilization_0" -objects $obj
  923. move_dashboard_gadget -name {utilization_1} -row 0 -col 0
  924. move_dashboard_gadget -name {power_1} -row 1 -col 0
  925. move_dashboard_gadget -name {drc_1} -row 2 -col 0
  926. move_dashboard_gadget -name {timing_1} -row 0 -col 1
  927. move_dashboard_gadget -name {utilization_2} -row 1 -col 1
  928. move_dashboard_gadget -name {methodology_1} -row 2 -col 1
    update_compile_order -fileset sources_1

RE: Cannot build hardware for i2c_demo - Added by Shawn Sebastian Pulle (ฌอน) 12 months ago

Hi Johan,

Thank you for the valuable feedback.
The root cause of this issue is absolute path definitions instead of relative file path definitions inside the tcl file.
Please replace your tcl file located at ".../demo/i2c_demo/hardware_design/vivado_tcl" folder with the attached file and update us with your findings.

RE: Cannot build hardware for i2c_demo - Added by Johan Henning 12 months ago

Hello Shawn,

Thanks for the updated .tcl file, this one works fine.
Besides the 8 critical warnings (which do not harm according to the link you've sent me) there is another warning: [IP_Flow 19-474] Invalid Parameter 'Component_Name'. It would be nice to solve that as wel in the future.
Another remark: the created project is called project_1. In case of other hardware projects (for example the adc_demo) the project is called adc_demo (which I like). In case of the gpio_demo the project is called zynq7000_gpio_demo. I prefer gpio_demo to be consistent.
Last remark (for this issue:-) ): It would be very nice if there was only one hardware configuration (.tcl / .xdc) that works for all demo's (I put that whish in the suggestions forum some time ago). That makes maintenance of the hardware much easier. And also combining partial models form the various demo's.

Regards!
johan.

Differences between original and new .tcl file:

RE: Cannot build hardware for i2c_demo - Added by Shawn Sebastian Pulle (ฌอน) 12 months ago

Hi Johan,

Thank you for the feedback.
1. Regarding warning: [IP_Flow 19-474] Invalid Parameter 'Component_Name'., we are unable to recreate this error from our end. Would it be possible to attach the full log so we can have an understanding at which point the warning is being thrown?
2. We will try to implement a consistent naming scheme for the projects created via tcl files in our future releases.
3. We are aware of the need and appeal of a hardware reference file that works with all of the demos. We will update you further on this matter on the feature request when we have come to a decision.

Best Regards,
Shawn

RE: Cannot build hardware for i2c_demo - Added by Johan Henning 12 months ago

Hello Shawn,

Interestingly I did not get the warning after rebuilding the hardware myself. It has solved itself somehow :-)
Below my logfile and the status messages.
Regards,
johan.
.

source i2c_demo.tcl
  1. proc checkRequiredFiles { origin_dir} {
  2. set status true
  3. set files [list \
  4. "xdc/My_Zybo-Z7-Master.xdc" \
  5. ]
  6. foreach ifile $files {
  7. if { ![file isfile $ifile] } {
  8. puts " Could not find remote file $ifile "
  9. set status false
  10. }
  11. }
  12. return $status
  13. }
  14. set origin_dir "."
  15. if { [info exists ::origin_dir_loc] } {
  16. set origin_dir $::origin_dir_loc
  17. }
  18. set xil_proj_name "project_1"
  19. if { [info exists ::user_project_name] } {
  20. set xil_proj_name $::user_project_name
  21. }
  22. variable script_file
  23. set script_file "i2c_demo.tcl"
  24. proc print_help {} {
  25. variable script_file
  26. puts "\nDescription:"
  27. puts "Recreate a Vivado project from this script. The created project will be"
  28. puts "functionally equivalent to the original project for which this script was"
  29. puts "generated. The script contains commands for creating a project, filesets,"
  30. puts "runs, adding/importing sources and setting properties on various objects.\n"
  31. puts "Syntax:"
  32. puts "$script_file"
  33. puts "$script_file -tclargs \[--origin_dir <path>\]"
  34. puts "$script_file -tclargs \[--project_name <name>\]"
  35. puts "$script_file -tclargs \[--help\]\n"
  36. puts "Usage:"
  37. puts "Name Description"
  38. puts "-------------------------------------------------------------------------"
  39. puts "\[--origin_dir <path>\] Determine source file paths wrt this path. Default"
  40. puts " origin_dir path value is \".\", otherwise, the value"
  41. puts " that was set with the \"-paths_relative_to\" switch"
  42. puts " when this script was generated.\n"
  43. puts "\[--project_name <name>\] Create project with the specified name. Default"
  44. puts " name is the name of the project from where this"
  45. puts " script was generated.\n"
  46. puts "\[--help\] Print help information for this script"
  47. puts "-------------------------------------------------------------------------\n"
  48. exit 0
  49. }
  50. if { $::argc > 0 } {
  51. for {set i 0} {$i < $::argc} {incr i} {
  52. set option [string trim [lindex $::argv $i]]
  53. switch regexp - $option {
  54. "--origin_dir" { incr i; set origin_dir [lindex $::argv $i] }
  55. "--project_name" { incr i; set xil_proj_name [lindex $::argv $i] }
  56. "--help" { print_help }
  57. default {
  58. if { [regexp {^-} $option] } {
  59. puts "ERROR: Unknown option '$option' specified, please type '$script_file -tclargs --help' for usage info.\n"
  60. return 1
  61. }
  62. }
  63. }
  64. }
  65. }
  66. set orig_proj_dir "[file normalize "$origin_dir/project_1"]"
  67. set validate_required 0
  68. if { $validate_required } {
  69. if { [checkRequiredFiles $origin_dir] } {
  70. puts "Tcl file $script_file is valid. All files required for project creation is accesable. "
  71. } else {
  72. puts "Tcl file $script_file is not valid. Not all files required for project creation is accesable. "
  73. return
  74. }
  75. }
  76. create_project ${_xil_proj_name_} ./${_xil_proj_name_} -part xc7z020clg400-1
    INFO: [IP_Flow 19-234] Refreshing IP repositories
    INFO: [IP_Flow 19-1704] No user IP repositories specified
    INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2020.2/data/ip'.
    create_project: Time (s): cpu = 00:00:04 ; elapsed = 00:00:07 . Memory (MB): peak = 1115.910 ; gain = 0.000
  77. set proj_dir [get_property directory [current_project]]
  78. set obj [current_project]
  79. set_property -name "board_part" -value "digilentinc.com:zybo-z7-20:part0:1.0" -objects $obj
  80. set_property -name "default_lib" -value "xil_defaultlib" -objects $obj
  81. set_property -name "enable_vhdl_2008" -value "1" -objects $obj
  82. set_property -name "ip_cache_permissions" -value "read write" -objects $obj
  83. set_property -name "ip_output_repo" -value "$proj_dir/${_xil_proj_name_}.cache/ip" -objects $obj
  84. set_property -name "mem.enable_memory_map_generation" -value "1" -objects $obj
  85. set_property -name "platform.board_id" -value "zybo-z7-20" -objects $obj
  86. set_property -name "sim.central_dir" -value "$proj_dir/${_xil_proj_name_}.ip_user_files" -objects $obj
  87. set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj
  88. set_property -name "simulator_language" -value "Mixed" -objects $obj
  89. set_property -name "target_language" -value "VHDL" -objects $obj
  90. if {[string equal [get_filesets -quiet sources_1] ""]} {
  91. create_fileset -srcset sources_1
  92. }
  93. set obj [get_filesets sources_1]
  94. set obj [get_filesets sources_1]
  95. set_property -name "top" -value "design_1_wrapper" -objects $obj
  96. if {[string equal [get_filesets -quiet constrs_1] ""]} {
  97. create_fileset -constrset constrs_1
  98. }
  99. set obj [get_filesets constrs_1]
  100. set file "[file normalize "xdc/My_Zybo-Z7-Master.xdc"]"
  101. set file_added [add_files -norecurse -fileset $obj [list $file]]
  102. set file "xdc/My_Zybo-Z7-Master.xdc"
  103. set file [file normalize $file]
  104. set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]]
  105. set_property -name "file_type" -value "XDC" -objects $file_obj
  106. set obj [get_filesets constrs_1]
  107. if {[string equal [get_filesets -quiet sim_1] ""]} {
  108. create_fileset -simset sim_1
  109. }
  110. set obj [get_filesets sim_1]
  111. set obj [get_filesets sim_1]
  112. set_property -name "hbs.configure_design_for_hier_access" -value "1" -objects $obj
  113. set_property -name "top" -value "design_1_wrapper" -objects $obj
  114. set_property -name "top_lib" -value "xil_defaultlib" -objects $obj
  115. set obj [get_filesets utils_1]
  116. set obj [get_filesets utils_1]
  117. proc cr_bd_design_1 { parentCell } {
  118. # CHANGE DESIGN NAME HERE
  119. set design_name design_1
  120. common::send_gid_msg -ssname BD::TCL -id 2010 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..."
  121. create_bd_design $design_name
  122. set bCheckIPsPassed 1
  123. ##################################################################
  124. # CHECK IPs
  125. ##################################################################
  126. set bCheckIPs 1
  127. if { $bCheckIPs == 1 } {
  128. set list_check_ips "\
  129. xilinx.com:ip:processing_system7:5.5\
  130. "
  131. set list_ips_missing ""
  132. common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
  133. foreach ip_vlnv $list_check_ips {
  134. set ip_obj [get_ipdefs -all $ip_vlnv]
  135. if { $ip_obj eq "" } {
  136. lappend list_ips_missing $ip_vlnv
  137. }
  138. }
  139. if { $list_ips_missing ne "" } {
  140. catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP to the project." }
  141. set bCheckIPsPassed 0
  142. }
  143. }
  144. if { $bCheckIPsPassed != 1 } {
  145. common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above."
  146. return 3
  147. }
  148. variable script_folder
  149. if { $parentCell eq "" } {
  150. set parentCell [get_bd_cells /]
  151. }
  152. # Get object for parentCell
  153. set parentObj [get_bd_cells $parentCell]
  154. if { $parentObj == "" } {
  155. catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
  156. return
  157. }
  158. # Make sure parentObj is hier blk
  159. set parentType [get_property TYPE $parentObj]
  160. if { $parentType ne "hier" } {
  161. catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
  162. return
  163. }
  164. # Save current instance; Restore later
  165. set oldCurInst [current_bd_instance .]
  166. # Set parent object as current
  167. current_bd_instance $parentObj
  168. # Create interface ports
  169. set DDR [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR ]
  170. set FIXED_IO [ create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 FIXED_IO ]
  171. set GPIO_0_0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 GPIO_0_0 ]
  172. # Create ports
  173. # Create instance: processing_system7_0, and set properties
  174. set processing_system7_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0 ]
  175. set_property -dict [ list \
  176. CONFIG.PCW_ACT_APU_PERIPHERAL_FREQMHZ {666.666687} \
  177. CONFIG.PCW_ACT_CAN_PERIPHERAL_FREQMHZ {10.000000} \
  178. CONFIG.PCW_ACT_DCI_PERIPHERAL_FREQMHZ {10.158730} \
  179. CONFIG.PCW_ACT_ENET0_PERIPHERAL_FREQMHZ {125.000000} \
  180. CONFIG.PCW_ACT_ENET1_PERIPHERAL_FREQMHZ {10.000000} \
  181. CONFIG.PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ {50.000000} \
  182. CONFIG.PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ {10.000000} \
  183. CONFIG.PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ {10.000000} \
  184. CONFIG.PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ {10.000000} \
  185. CONFIG.PCW_ACT_PCAP_PERIPHERAL_FREQMHZ {200.000000} \
  186. CONFIG.PCW_ACT_QSPI_PERIPHERAL_FREQMHZ {200.000000} \
  187. CONFIG.PCW_ACT_SDIO_PERIPHERAL_FREQMHZ {10.000000} \
  188. CONFIG.PCW_ACT_SMC_PERIPHERAL_FREQMHZ {10.000000} \
  189. CONFIG.PCW_ACT_SPI_PERIPHERAL_FREQMHZ {10.000000} \
  190. CONFIG.PCW_ACT_TPIU_PERIPHERAL_FREQMHZ {200.000000} \
  191. CONFIG.PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ {111.111115} \
  192. CONFIG.PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ {111.111115} \
  193. CONFIG.PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ {111.111115} \
  194. CONFIG.PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ {111.111115} \
  195. CONFIG.PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ {111.111115} \
  196. CONFIG.PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ {111.111115} \
  197. CONFIG.PCW_ACT_UART_PERIPHERAL_FREQMHZ {100.000000} \
  198. CONFIG.PCW_ACT_WDT_PERIPHERAL_FREQMHZ {111.111115} \
  199. CONFIG.PCW_APU_CLK_RATIO_ENABLE {6:2:1} \
  200. CONFIG.PCW_APU_PERIPHERAL_FREQMHZ {667} \
  201. CONFIG.PCW_ARMPLL_CTRL_FBDIV {40} \
  202. CONFIG.PCW_CAN_PERIPHERAL_DIVISOR0 {1} \
  203. CONFIG.PCW_CAN_PERIPHERAL_DIVISOR1 {1} \
  204. CONFIG.PCW_CLK0_FREQ {50000000} \
  205. CONFIG.PCW_CLK1_FREQ {10000000} \
  206. CONFIG.PCW_CLK2_FREQ {10000000} \
  207. CONFIG.PCW_CLK3_FREQ {10000000} \
  208. CONFIG.PCW_CPU_CPU_6X4X_MAX_RANGE {667} \
  209. CONFIG.PCW_CPU_CPU_PLL_FREQMHZ {1333.333} \
  210. CONFIG.PCW_CPU_PERIPHERAL_CLKSRC {ARM PLL} \
  211. CONFIG.PCW_CPU_PERIPHERAL_DIVISOR0 {2} \
  212. CONFIG.PCW_CRYSTAL_PERIPHERAL_FREQMHZ {33.333333} \
  213. CONFIG.PCW_DCI_PERIPHERAL_CLKSRC {DDR PLL} \
  214. CONFIG.PCW_DCI_PERIPHERAL_DIVISOR0 {15} \
  215. CONFIG.PCW_DCI_PERIPHERAL_DIVISOR1 {7} \
  216. CONFIG.PCW_DCI_PERIPHERAL_FREQMHZ {10.159} \
  217. CONFIG.PCW_DDRPLL_CTRL_FBDIV {32} \
  218. CONFIG.PCW_DDR_DDR_PLL_FREQMHZ {1066.667} \
  219. CONFIG.PCW_DDR_HPRLPR_QUEUE_PARTITION {HPR/LPR} \
  220. CONFIG.PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL {15} \
  221. CONFIG.PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL {2} \
  222. CONFIG.PCW_DDR_PERIPHERAL_CLKSRC {DDR PLL} \
  223. CONFIG.PCW_DDR_PERIPHERAL_DIVISOR0 {2} \
  224. CONFIG.PCW_DDR_PORT0_HPR_ENABLE {0} \
  225. CONFIG.PCW_DDR_PORT1_HPR_ENABLE {0} \
  226. CONFIG.PCW_DDR_PORT2_HPR_ENABLE {0} \
  227. CONFIG.PCW_DDR_PORT3_HPR_ENABLE {0} \
  228. CONFIG.PCW_DDR_RAM_HIGHADDR {0x3FFFFFFF} \
  229. CONFIG.PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL {2} \
  230. CONFIG.PCW_ENET0_ENET0_IO {MIO 16 .. 27} \
  231. CONFIG.PCW_ENET0_GRP_MDIO_ENABLE {1} \
  232. CONFIG.PCW_ENET0_GRP_MDIO_IO {MIO 52 .. 53} \
  233. CONFIG.PCW_ENET0_PERIPHERAL_CLKSRC {IO PLL} \
  234. CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR0 {8} \
  235. CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR1 {1} \
  236. CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {1} \
  237. CONFIG.PCW_ENET0_PERIPHERAL_FREQMHZ {1000 Mbps} \
  238. CONFIG.PCW_ENET0_RESET_ENABLE {0} \
  239. CONFIG.PCW_ENET1_GRP_MDIO_ENABLE {0} \
  240. CONFIG.PCW_ENET1_PERIPHERAL_CLKSRC {IO PLL} \
  241. CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR0 {1} \
  242. CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR1 {1} \
  243. CONFIG.PCW_ENET1_PERIPHERAL_ENABLE {0} \
  244. CONFIG.PCW_ENET1_PERIPHERAL_FREQMHZ {1000 Mbps} \
  245. CONFIG.PCW_ENET1_RESET_ENABLE {0} \
  246. CONFIG.PCW_ENET_RESET_ENABLE {1} \
  247. CONFIG.PCW_ENET_RESET_POLARITY {Active Low} \
  248. CONFIG.PCW_ENET_RESET_SELECT {Share reset pin} \
  249. CONFIG.PCW_EN_4K_TIMER {0} \
  250. CONFIG.PCW_EN_EMIO_ENET0 {0} \
  251. CONFIG.PCW_EN_EMIO_GPIO {1} \
  252. CONFIG.PCW_EN_EMIO_I2C0 {0} \
  253. CONFIG.PCW_EN_EMIO_I2C1 {0} \
  254. CONFIG.PCW_EN_ENET0 {1} \
  255. CONFIG.PCW_EN_GPIO {1} \
  256. CONFIG.PCW_EN_I2C0 {1} \
  257. CONFIG.PCW_EN_I2C1 {1} \
  258. CONFIG.PCW_EN_QSPI {1} \
  259. CONFIG.PCW_EN_SDIO0 {0} \
  260. CONFIG.PCW_EN_UART1 {1} \
  261. CONFIG.PCW_EN_USB0 {0} \
  262. CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR0 {5} \
  263. CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR1 {4} \
  264. CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR0 {1} \
  265. CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR1 {1} \
  266. CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR0 {1} \
  267. CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR1 {1} \
  268. CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR0 {1} \
  269. CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR1 {1} \
  270. CONFIG.PCW_FPGA_FCLK0_ENABLE {1} \
  271. CONFIG.PCW_FPGA_FCLK1_ENABLE {0} \
  272. CONFIG.PCW_FPGA_FCLK2_ENABLE {0} \
  273. CONFIG.PCW_FPGA_FCLK3_ENABLE {0} \
  274. CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {1} \
  275. CONFIG.PCW_GPIO_EMIO_GPIO_IO {26} \
  276. CONFIG.PCW_GPIO_EMIO_GPIO_WIDTH {26} \
  277. CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1} \
  278. CONFIG.PCW_GPIO_MIO_GPIO_IO {MIO} \
  279. CONFIG.PCW_GPIO_PERIPHERAL_ENABLE {0} \
  280. CONFIG.PCW_I2C0_GRP_INT_ENABLE {1} \
  281. CONFIG.PCW_I2C0_GRP_INT_IO {EMIO} \
  282. CONFIG.PCW_I2C0_I2C0_IO {MIO 14 .. 15} \
  283. CONFIG.PCW_I2C0_PERIPHERAL_ENABLE {1} \
  284. CONFIG.PCW_I2C0_RESET_ENABLE {0} \
  285. CONFIG.PCW_I2C1_GRP_INT_ENABLE {1} \
  286. CONFIG.PCW_I2C1_GRP_INT_IO {EMIO} \
  287. CONFIG.PCW_I2C1_I2C1_IO {MIO 12 .. 13} \
  288. CONFIG.PCW_I2C1_PERIPHERAL_ENABLE {1} \
  289. CONFIG.PCW_I2C1_RESET_ENABLE {0} \
  290. CONFIG.PCW_I2C_PERIPHERAL_FREQMHZ {111.111115} \
  291. CONFIG.PCW_I2C_RESET_ENABLE {1} \
  292. CONFIG.PCW_I2C_RESET_SELECT {Share reset pin} \
  293. CONFIG.PCW_IOPLL_CTRL_FBDIV {30} \
  294. CONFIG.PCW_IO_IO_PLL_FREQMHZ {1000.000} \
  295. CONFIG.PCW_IRQ_F2P_MODE {DIRECT} \
  296. CONFIG.PCW_MIO_0_DIRECTION {inout} \
  297. CONFIG.PCW_MIO_0_IOTYPE {LVCMOS 3.3V} \
  298. CONFIG.PCW_MIO_0_PULLUP {enabled} \
  299. CONFIG.PCW_MIO_0_SLEW {slow} \
  300. CONFIG.PCW_MIO_10_DIRECTION {inout} \
  301. CONFIG.PCW_MIO_10_IOTYPE {LVCMOS 3.3V} \
  302. CONFIG.PCW_MIO_10_PULLUP {enabled} \
  303. CONFIG.PCW_MIO_10_SLEW {slow} \
  304. CONFIG.PCW_MIO_11_DIRECTION {inout} \
  305. CONFIG.PCW_MIO_11_IOTYPE {LVCMOS 3.3V} \
  306. CONFIG.PCW_MIO_11_PULLUP {enabled} \
  307. CONFIG.PCW_MIO_11_SLEW {slow} \
  308. CONFIG.PCW_MIO_12_DIRECTION {inout} \
  309. CONFIG.PCW_MIO_12_IOTYPE {LVCMOS 3.3V} \
  310. CONFIG.PCW_MIO_12_PULLUP {enabled} \
  311. CONFIG.PCW_MIO_12_SLEW {slow} \
  312. CONFIG.PCW_MIO_13_DIRECTION {inout} \
  313. CONFIG.PCW_MIO_13_IOTYPE {LVCMOS 3.3V} \
  314. CONFIG.PCW_MIO_13_PULLUP {enabled} \
  315. CONFIG.PCW_MIO_13_SLEW {slow} \
  316. CONFIG.PCW_MIO_14_DIRECTION {inout} \
  317. CONFIG.PCW_MIO_14_IOTYPE {LVCMOS 3.3V} \
  318. CONFIG.PCW_MIO_14_PULLUP {enabled} \
  319. CONFIG.PCW_MIO_14_SLEW {slow} \
  320. CONFIG.PCW_MIO_15_DIRECTION {inout} \
  321. CONFIG.PCW_MIO_15_IOTYPE {LVCMOS 3.3V} \
  322. CONFIG.PCW_MIO_15_PULLUP {enabled} \
  323. CONFIG.PCW_MIO_15_SLEW {slow} \
  324. CONFIG.PCW_MIO_16_DIRECTION {out} \
  325. CONFIG.PCW_MIO_16_IOTYPE {LVCMOS 1.8V} \
  326. CONFIG.PCW_MIO_16_PULLUP {enabled} \
  327. CONFIG.PCW_MIO_16_SLEW {fast} \
  328. CONFIG.PCW_MIO_17_DIRECTION {out} \
  329. CONFIG.PCW_MIO_17_IOTYPE {LVCMOS 1.8V} \
  330. CONFIG.PCW_MIO_17_PULLUP {enabled} \
  331. CONFIG.PCW_MIO_17_SLEW {fast} \
  332. CONFIG.PCW_MIO_18_DIRECTION {out} \
  333. CONFIG.PCW_MIO_18_IOTYPE {LVCMOS 1.8V} \
  334. CONFIG.PCW_MIO_18_PULLUP {enabled} \
  335. CONFIG.PCW_MIO_18_SLEW {fast} \
  336. CONFIG.PCW_MIO_19_DIRECTION {out} \
  337. CONFIG.PCW_MIO_19_IOTYPE {LVCMOS 1.8V} \
  338. CONFIG.PCW_MIO_19_PULLUP {enabled} \
  339. CONFIG.PCW_MIO_19_SLEW {fast} \
  340. CONFIG.PCW_MIO_1_DIRECTION {out} \
  341. CONFIG.PCW_MIO_1_IOTYPE {LVCMOS 3.3V} \
  342. CONFIG.PCW_MIO_1_PULLUP {enabled} \
  343. CONFIG.PCW_MIO_1_SLEW {slow} \
  344. CONFIG.PCW_MIO_20_DIRECTION {out} \
  345. CONFIG.PCW_MIO_20_IOTYPE {LVCMOS 1.8V} \
  346. CONFIG.PCW_MIO_20_PULLUP {enabled} \
  347. CONFIG.PCW_MIO_20_SLEW {fast} \
  348. CONFIG.PCW_MIO_21_DIRECTION {out} \
  349. CONFIG.PCW_MIO_21_IOTYPE {LVCMOS 1.8V} \
  350. CONFIG.PCW_MIO_21_PULLUP {enabled} \
  351. CONFIG.PCW_MIO_21_SLEW {fast} \
  352. CONFIG.PCW_MIO_22_DIRECTION {in} \
  353. CONFIG.PCW_MIO_22_IOTYPE {LVCMOS 1.8V} \
  354. CONFIG.PCW_MIO_22_PULLUP {enabled} \
  355. CONFIG.PCW_MIO_22_SLEW {fast} \
  356. CONFIG.PCW_MIO_23_DIRECTION {in} \
  357. CONFIG.PCW_MIO_23_IOTYPE {LVCMOS 1.8V} \
  358. CONFIG.PCW_MIO_23_PULLUP {enabled} \
  359. CONFIG.PCW_MIO_23_SLEW {fast} \
  360. CONFIG.PCW_MIO_24_DIRECTION {in} \
  361. CONFIG.PCW_MIO_24_IOTYPE {LVCMOS 1.8V} \
  362. CONFIG.PCW_MIO_24_PULLUP {enabled} \
  363. CONFIG.PCW_MIO_24_SLEW {fast} \
  364. CONFIG.PCW_MIO_25_DIRECTION {in} \
  365. CONFIG.PCW_MIO_25_IOTYPE {LVCMOS 1.8V} \
  366. CONFIG.PCW_MIO_25_PULLUP {enabled} \
  367. CONFIG.PCW_MIO_25_SLEW {fast} \
  368. CONFIG.PCW_MIO_26_DIRECTION {in} \
  369. CONFIG.PCW_MIO_26_IOTYPE {LVCMOS 1.8V} \
  370. CONFIG.PCW_MIO_26_PULLUP {enabled} \
  371. CONFIG.PCW_MIO_26_SLEW {fast} \
  372. CONFIG.PCW_MIO_27_DIRECTION {in} \
  373. CONFIG.PCW_MIO_27_IOTYPE {LVCMOS 1.8V} \
  374. CONFIG.PCW_MIO_27_PULLUP {enabled} \
  375. CONFIG.PCW_MIO_27_SLEW {fast} \
  376. CONFIG.PCW_MIO_28_DIRECTION {inout} \
  377. CONFIG.PCW_MIO_28_IOTYPE {LVCMOS 1.8V} \
  378. CONFIG.PCW_MIO_28_PULLUP {enabled} \
  379. CONFIG.PCW_MIO_28_SLEW {fast} \
  380. CONFIG.PCW_MIO_29_DIRECTION {inout} \
  381. CONFIG.PCW_MIO_29_IOTYPE {LVCMOS 1.8V} \
  382. CONFIG.PCW_MIO_29_PULLUP {enabled} \
  383. CONFIG.PCW_MIO_29_SLEW {fast} \
  384. CONFIG.PCW_MIO_2_DIRECTION {inout} \
  385. CONFIG.PCW_MIO_2_IOTYPE {LVCMOS 3.3V} \
  386. CONFIG.PCW_MIO_2_PULLUP {disabled} \
  387. CONFIG.PCW_MIO_2_SLEW {slow} \
  388. CONFIG.PCW_MIO_30_DIRECTION {inout} \
  389. CONFIG.PCW_MIO_30_IOTYPE {LVCMOS 1.8V} \
  390. CONFIG.PCW_MIO_30_PULLUP {enabled} \
  391. CONFIG.PCW_MIO_30_SLEW {fast} \
  392. CONFIG.PCW_MIO_31_DIRECTION {inout} \
  393. CONFIG.PCW_MIO_31_IOTYPE {LVCMOS 1.8V} \
  394. CONFIG.PCW_MIO_31_PULLUP {enabled} \
  395. CONFIG.PCW_MIO_31_SLEW {fast} \
  396. CONFIG.PCW_MIO_32_DIRECTION {inout} \
  397. CONFIG.PCW_MIO_32_IOTYPE {LVCMOS 1.8V} \
  398. CONFIG.PCW_MIO_32_PULLUP {enabled} \
  399. CONFIG.PCW_MIO_32_SLEW {fast} \
  400. CONFIG.PCW_MIO_33_DIRECTION {inout} \
  401. CONFIG.PCW_MIO_33_IOTYPE {LVCMOS 1.8V} \
  402. CONFIG.PCW_MIO_33_PULLUP {enabled} \
  403. CONFIG.PCW_MIO_33_SLEW {fast} \
  404. CONFIG.PCW_MIO_34_DIRECTION {inout} \
  405. CONFIG.PCW_MIO_34_IOTYPE {LVCMOS 1.8V} \
  406. CONFIG.PCW_MIO_34_PULLUP {enabled} \
  407. CONFIG.PCW_MIO_34_SLEW {fast} \
  408. CONFIG.PCW_MIO_35_DIRECTION {inout} \
  409. CONFIG.PCW_MIO_35_IOTYPE {LVCMOS 1.8V} \
  410. CONFIG.PCW_MIO_35_PULLUP {enabled} \
  411. CONFIG.PCW_MIO_35_SLEW {fast} \
  412. CONFIG.PCW_MIO_36_DIRECTION {inout} \
  413. CONFIG.PCW_MIO_36_IOTYPE {LVCMOS 1.8V} \
  414. CONFIG.PCW_MIO_36_PULLUP {enabled} \
  415. CONFIG.PCW_MIO_36_SLEW {fast} \
  416. CONFIG.PCW_MIO_37_DIRECTION {inout} \
  417. CONFIG.PCW_MIO_37_IOTYPE {LVCMOS 1.8V} \
  418. CONFIG.PCW_MIO_37_PULLUP {enabled} \
  419. CONFIG.PCW_MIO_37_SLEW {fast} \
  420. CONFIG.PCW_MIO_38_DIRECTION {inout} \
  421. CONFIG.PCW_MIO_38_IOTYPE {LVCMOS 1.8V} \
  422. CONFIG.PCW_MIO_38_PULLUP {enabled} \
  423. CONFIG.PCW_MIO_38_SLEW {fast} \
  424. CONFIG.PCW_MIO_39_DIRECTION {inout} \
  425. CONFIG.PCW_MIO_39_IOTYPE {LVCMOS 1.8V} \
  426. CONFIG.PCW_MIO_39_PULLUP {enabled} \
  427. CONFIG.PCW_MIO_39_SLEW {fast} \
  428. CONFIG.PCW_MIO_3_DIRECTION {inout} \
  429. CONFIG.PCW_MIO_3_IOTYPE {LVCMOS 3.3V} \
  430. CONFIG.PCW_MIO_3_PULLUP {disabled} \
  431. CONFIG.PCW_MIO_3_SLEW {slow} \
  432. CONFIG.PCW_MIO_40_DIRECTION {inout} \
  433. CONFIG.PCW_MIO_40_IOTYPE {LVCMOS 1.8V} \
  434. CONFIG.PCW_MIO_40_PULLUP {enabled} \
  435. CONFIG.PCW_MIO_40_SLEW {slow} \
  436. CONFIG.PCW_MIO_41_DIRECTION {inout} \
  437. CONFIG.PCW_MIO_41_IOTYPE {LVCMOS 1.8V} \
  438. CONFIG.PCW_MIO_41_PULLUP {enabled} \
  439. CONFIG.PCW_MIO_41_SLEW {slow} \
  440. CONFIG.PCW_MIO_42_DIRECTION {inout} \
  441. CONFIG.PCW_MIO_42_IOTYPE {LVCMOS 1.8V} \
  442. CONFIG.PCW_MIO_42_PULLUP {enabled} \
  443. CONFIG.PCW_MIO_42_SLEW {slow} \
  444. CONFIG.PCW_MIO_43_DIRECTION {inout} \
  445. CONFIG.PCW_MIO_43_IOTYPE {LVCMOS 1.8V} \
  446. CONFIG.PCW_MIO_43_PULLUP {enabled} \
  447. CONFIG.PCW_MIO_43_SLEW {slow} \
  448. CONFIG.PCW_MIO_44_DIRECTION {inout} \
  449. CONFIG.PCW_MIO_44_IOTYPE {LVCMOS 1.8V} \
  450. CONFIG.PCW_MIO_44_PULLUP {enabled} \
  451. CONFIG.PCW_MIO_44_SLEW {slow} \
  452. CONFIG.PCW_MIO_45_DIRECTION {inout} \
  453. CONFIG.PCW_MIO_45_IOTYPE {LVCMOS 1.8V} \
  454. CONFIG.PCW_MIO_45_PULLUP {enabled} \
  455. CONFIG.PCW_MIO_45_SLEW {slow} \
  456. CONFIG.PCW_MIO_46_DIRECTION {out} \
  457. CONFIG.PCW_MIO_46_IOTYPE {LVCMOS 1.8V} \
  458. CONFIG.PCW_MIO_46_PULLUP {enabled} \
  459. CONFIG.PCW_MIO_46_SLEW {slow} \
  460. CONFIG.PCW_MIO_47_DIRECTION {in} \
  461. CONFIG.PCW_MIO_47_IOTYPE {LVCMOS 1.8V} \
  462. CONFIG.PCW_MIO_47_PULLUP {enabled} \
  463. CONFIG.PCW_MIO_47_SLEW {slow} \
  464. CONFIG.PCW_MIO_48_DIRECTION {out} \
  465. CONFIG.PCW_MIO_48_IOTYPE {LVCMOS 1.8V} \
  466. CONFIG.PCW_MIO_48_PULLUP {enabled} \
  467. CONFIG.PCW_MIO_48_SLEW {slow} \
  468. CONFIG.PCW_MIO_49_DIRECTION {in} \
  469. CONFIG.PCW_MIO_49_IOTYPE {LVCMOS 1.8V} \
  470. CONFIG.PCW_MIO_49_PULLUP {enabled} \
  471. CONFIG.PCW_MIO_49_SLEW {slow} \
  472. CONFIG.PCW_MIO_4_DIRECTION {inout} \
  473. CONFIG.PCW_MIO_4_IOTYPE {LVCMOS 3.3V} \
  474. CONFIG.PCW_MIO_4_PULLUP {disabled} \
  475. CONFIG.PCW_MIO_4_SLEW {slow} \
  476. CONFIG.PCW_MIO_50_DIRECTION {inout} \
  477. CONFIG.PCW_MIO_50_IOTYPE {LVCMOS 1.8V} \
  478. CONFIG.PCW_MIO_50_PULLUP {enabled} \
  479. CONFIG.PCW_MIO_50_SLEW {slow} \
  480. CONFIG.PCW_MIO_51_DIRECTION {inout} \
  481. CONFIG.PCW_MIO_51_IOTYPE {LVCMOS 1.8V} \
  482. CONFIG.PCW_MIO_51_PULLUP {enabled} \
  483. CONFIG.PCW_MIO_51_SLEW {slow} \
  484. CONFIG.PCW_MIO_52_DIRECTION {out} \
  485. CONFIG.PCW_MIO_52_IOTYPE {LVCMOS 1.8V} \
  486. CONFIG.PCW_MIO_52_PULLUP {enabled} \
  487. CONFIG.PCW_MIO_52_SLEW {slow} \
  488. CONFIG.PCW_MIO_53_DIRECTION {inout} \
  489. CONFIG.PCW_MIO_53_IOTYPE {LVCMOS 1.8V} \
  490. CONFIG.PCW_MIO_53_PULLUP {enabled} \
  491. CONFIG.PCW_MIO_53_SLEW {slow} \
  492. CONFIG.PCW_MIO_5_DIRECTION {inout} \
  493. CONFIG.PCW_MIO_5_IOTYPE {LVCMOS 3.3V} \
  494. CONFIG.PCW_MIO_5_PULLUP {disabled} \
  495. CONFIG.PCW_MIO_5_SLEW {slow} \
  496. CONFIG.PCW_MIO_6_DIRECTION {out} \
  497. CONFIG.PCW_MIO_6_IOTYPE {LVCMOS 3.3V} \
  498. CONFIG.PCW_MIO_6_PULLUP {disabled} \
  499. CONFIG.PCW_MIO_6_SLEW {slow} \
  500. CONFIG.PCW_MIO_7_DIRECTION {out} \
  501. CONFIG.PCW_MIO_7_IOTYPE {LVCMOS 3.3V} \
  502. CONFIG.PCW_MIO_7_PULLUP {disabled} \
  503. CONFIG.PCW_MIO_7_SLEW {slow} \
  504. CONFIG.PCW_MIO_8_DIRECTION {out} \
  505. CONFIG.PCW_MIO_8_IOTYPE {LVCMOS 3.3V} \
  506. CONFIG.PCW_MIO_8_PULLUP {disabled} \
  507. CONFIG.PCW_MIO_8_SLEW {slow} \
  508. CONFIG.PCW_MIO_9_DIRECTION {inout} \
  509. CONFIG.PCW_MIO_9_IOTYPE {LVCMOS 3.3V} \
  510. CONFIG.PCW_MIO_9_PULLUP {enabled} \
  511. CONFIG.PCW_MIO_9_SLEW {slow} \
  512. CONFIG.PCW_MIO_TREE_PERIPHERALS {GPIO#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#GPIO#Quad SPI Flash#GPIO#GPIO#GPIO#I2C 1#I2C 1#I2C 0#I2C 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#UART 1#UART 1#GPIO#GPIO#Enet 0#Enet 0} \
  513. CONFIG.PCW_MIO_TREE_SIGNALS {gpio0#qspi0_ss_b#qspi0_io0#qspi0_io1#qspi0_io2#qspi0_io3/HOLD_B#qspi0_sclk#gpio7#qspi_fbclk#gpio9#gpio10#gpio11#scl#sda#scl#sda#tx_clk#txd0#txd1#txd2#txd3#tx_ctl#rx_clk#rxd0#rxd1#rxd2#rxd3#rx_ctl#gpio28#gpio29#gpio30#gpio31#gpio32#gpio33#gpio34#gpio35#gpio36#gpio37#gpio38#gpio39#gpio40#gpio41#gpio42#gpio43#gpio44#gpio45#gpio46#gpio47#tx#rx#gpio50#gpio51#mdc#mdio} \
  514. CONFIG.PCW_NAND_GRP_D8_ENABLE {0} \
  515. CONFIG.PCW_NAND_PERIPHERAL_ENABLE {0} \
  516. CONFIG.PCW_NOR_GRP_A25_ENABLE {0} \
  517. CONFIG.PCW_NOR_GRP_CS0_ENABLE {0} \
  518. CONFIG.PCW_NOR_GRP_CS1_ENABLE {0} \
  519. CONFIG.PCW_NOR_GRP_SRAM_CS0_ENABLE {0} \
  520. CONFIG.PCW_NOR_GRP_SRAM_CS1_ENABLE {0} \
  521. CONFIG.PCW_NOR_GRP_SRAM_INT_ENABLE {0} \
  522. CONFIG.PCW_NOR_PERIPHERAL_ENABLE {0} \
  523. CONFIG.PCW_OVERRIDE_BASIC_CLOCK {0} \
  524. CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY0 {0.221} \
  525. CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY1 {0.222} \
  526. CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY2 {0.217} \
  527. CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY3 {0.244} \
  528. CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_0 {-0.050} \
  529. CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_1 {-0.044} \
  530. CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_2 {-0.035} \
  531. CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_3 {-0.100} \
  532. CONFIG.PCW_PCAP_PERIPHERAL_CLKSRC {IO PLL} \
  533. CONFIG.PCW_PCAP_PERIPHERAL_DIVISOR0 {5} \
  534. CONFIG.PCW_PCAP_PERIPHERAL_FREQMHZ {200} \
  535. CONFIG.PCW_PJTAG_PERIPHERAL_ENABLE {0} \
  536. CONFIG.PCW_PLL_BYPASSMODE_ENABLE {0} \
  537. CONFIG.PCW_PRESET_BANK0_VOLTAGE {LVCMOS 3.3V} \
  538. CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 1.8V} \
  539. CONFIG.PCW_QSPI_GRP_FBCLK_ENABLE {1} \
  540. CONFIG.PCW_QSPI_GRP_FBCLK_IO {MIO 8} \
  541. CONFIG.PCW_QSPI_GRP_IO1_ENABLE {0} \
  542. CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE {1} \
  543. CONFIG.PCW_QSPI_GRP_SINGLE_SS_IO {MIO 1 .. 6} \
  544. CONFIG.PCW_QSPI_GRP_SS1_ENABLE {0} \
  545. CONFIG.PCW_QSPI_INTERNAL_HIGHADDRESS {0xFCFFFFFF} \
  546. CONFIG.PCW_QSPI_PERIPHERAL_CLKSRC {IO PLL} \
  547. CONFIG.PCW_QSPI_PERIPHERAL_DIVISOR0 {5} \
  548. CONFIG.PCW_QSPI_PERIPHERAL_ENABLE {1} \
  549. CONFIG.PCW_QSPI_PERIPHERAL_FREQMHZ {200} \
  550. CONFIG.PCW_QSPI_QSPI_IO {MIO 1 .. 6} \
  551. CONFIG.PCW_SD0_GRP_CD_ENABLE {0} \
  552. CONFIG.PCW_SD0_GRP_CD_IO {<Select>} \
  553. CONFIG.PCW_SD0_GRP_POW_ENABLE {0} \
  554. CONFIG.PCW_SD0_GRP_WP_ENABLE {0} \
  555. CONFIG.PCW_SD0_PERIPHERAL_ENABLE {0} \
  556. CONFIG.PCW_SD0_SD0_IO {<Select>} \
  557. CONFIG.PCW_SDIO_PERIPHERAL_CLKSRC {IO PLL} \
  558. CONFIG.PCW_SDIO_PERIPHERAL_DIVISOR0 {1} \
  559. CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ {50} \
  560. CONFIG.PCW_SDIO_PERIPHERAL_VALID {0} \
  561. CONFIG.PCW_SINGLE_QSPI_DATA_MODE {x4} \
  562. CONFIG.PCW_SMC_PERIPHERAL_CLKSRC {IO PLL} \
  563. CONFIG.PCW_SMC_PERIPHERAL_DIVISOR0 {1} \
  564. CONFIG.PCW_SMC_PERIPHERAL_FREQMHZ {100} \
  565. CONFIG.PCW_SPI_PERIPHERAL_DIVISOR0 {1} \
  566. CONFIG.PCW_TPIU_PERIPHERAL_CLKSRC {External} \
  567. CONFIG.PCW_TPIU_PERIPHERAL_DIVISOR0 {1} \
  568. CONFIG.PCW_TPIU_PERIPHERAL_FREQMHZ {200} \
  569. CONFIG.PCW_UART1_BAUD_RATE {115200} \
  570. CONFIG.PCW_UART1_GRP_FULL_ENABLE {0} \
  571. CONFIG.PCW_UART1_PERIPHERAL_ENABLE {1} \
  572. CONFIG.PCW_UART1_UART1_IO {MIO 48 .. 49} \
  573. CONFIG.PCW_UART_PERIPHERAL_CLKSRC {IO PLL} \
  574. CONFIG.PCW_UART_PERIPHERAL_DIVISOR0 {10} \
  575. CONFIG.PCW_UART_PERIPHERAL_FREQMHZ {100} \
  576. CONFIG.PCW_UART_PERIPHERAL_VALID {1} \
  577. CONFIG.PCW_UIPARAM_ACT_DDR_FREQ_MHZ {533.333374} \
  578. CONFIG.PCW_UIPARAM_DDR_ADV_ENABLE {0} \
  579. CONFIG.PCW_UIPARAM_DDR_AL {0} \
  580. CONFIG.PCW_UIPARAM_DDR_BANK_ADDR_COUNT {3} \
  581. CONFIG.PCW_UIPARAM_DDR_BL {8} \
  582. CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0 {0.221} \
  583. CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1 {0.222} \
  584. CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2 {0.217} \
  585. CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3 {0.244} \
  586. CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH {32 Bit} \
  587. CONFIG.PCW_UIPARAM_DDR_CL {7} \
  588. CONFIG.PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM {18.8} \
  589. CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH {80.4535} \
  590. CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY {160} \
  591. CONFIG.PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM {18.8} \
  592. CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH {80.4535} \
  593. CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY {160} \
  594. CONFIG.PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM {18.8} \
  595. CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH {80.4535} \
  596. CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY {160} \
  597. CONFIG.PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM {18.8} \
  598. CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH {80.4535} \
  599. CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY {160} \
  600. CONFIG.PCW_UIPARAM_DDR_CLOCK_STOP_EN {0} \
  601. CONFIG.PCW_UIPARAM_DDR_COL_ADDR_COUNT {10} \
  602. CONFIG.PCW_UIPARAM_DDR_CWL {6} \
  603. CONFIG.PCW_UIPARAM_DDR_DEVICE_CAPACITY {4096 MBits} \
  604. CONFIG.PCW_UIPARAM_DDR_DQS_0_LENGTH_MM {22.8} \
  605. CONFIG.PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH {105.056} \
  606. CONFIG.PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY {160} \
  607. CONFIG.PCW_UIPARAM_DDR_DQS_1_LENGTH_MM {27.9} \
  608. CONFIG.PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH {66.904} \
  609. CONFIG.PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY {160} \
  610. CONFIG.PCW_UIPARAM_DDR_DQS_2_LENGTH_MM {22.9} \
  611. CONFIG.PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH {89.1715} \
  612. CONFIG.PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY {160} \
  613. CONFIG.PCW_UIPARAM_DDR_DQS_3_LENGTH_MM {29.4} \
  614. CONFIG.PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH {113.63} \
  615. CONFIG.PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY {160} \
  616. CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 {-0.050} \
  617. CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 {-0.044} \
  618. CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 {-0.035} \
  619. CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 {-0.100} \
  620. CONFIG.PCW_UIPARAM_DDR_DQ_0_LENGTH_MM {22.8} \
  621. CONFIG.PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH {98.503} \
  622. CONFIG.PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY {160} \
  623. CONFIG.PCW_UIPARAM_DDR_DQ_1_LENGTH_MM {27.9} \
  624. CONFIG.PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH {68.5855} \
  625. CONFIG.PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY {160} \
  626. CONFIG.PCW_UIPARAM_DDR_DQ_2_LENGTH_MM {22.9} \
  627. CONFIG.PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH {90.295} \
  628. CONFIG.PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY {160} \
  629. CONFIG.PCW_UIPARAM_DDR_DQ_3_LENGTH_MM {29.4} \
  630. CONFIG.PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH {103.977} \
  631. CONFIG.PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY {160} \
  632. CONFIG.PCW_UIPARAM_DDR_DRAM_WIDTH {16 Bits} \
  633. CONFIG.PCW_UIPARAM_DDR_ECC {Disabled} \
  634. CONFIG.PCW_UIPARAM_DDR_ENABLE {1} \
  635. CONFIG.PCW_UIPARAM_DDR_FREQ_MHZ {533.333333} \
  636. CONFIG.PCW_UIPARAM_DDR_HIGH_TEMP {Normal (0-85)} \
  637. CONFIG.PCW_UIPARAM_DDR_MEMORY_TYPE {DDR 3 (Low Voltage)} \
  638. CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41K256M16 RE-125} \
  639. CONFIG.PCW_UIPARAM_DDR_ROW_ADDR_COUNT {15} \
  640. CONFIG.PCW_UIPARAM_DDR_SPEED_BIN {DDR3_1066F} \
  641. CONFIG.PCW_UIPARAM_DDR_TRAIN_DATA_EYE {1} \
  642. CONFIG.PCW_UIPARAM_DDR_TRAIN_READ_GATE {1} \
  643. CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL {1} \
  644. CONFIG.PCW_UIPARAM_DDR_T_FAW {40.0} \
  645. CONFIG.PCW_UIPARAM_DDR_T_RAS_MIN {35.0} \
  646. CONFIG.PCW_UIPARAM_DDR_T_RC {48.75} \
  647. CONFIG.PCW_UIPARAM_DDR_T_RCD {7} \
  648. CONFIG.PCW_UIPARAM_DDR_T_RP {7} \
  649. CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF {0} \
  650. CONFIG.PCW_USB0_PERIPHERAL_ENABLE {0} \
  651. CONFIG.PCW_USB0_PERIPHERAL_FREQMHZ {60} \
  652. CONFIG.PCW_USB0_RESET_ENABLE {1} \
  653. CONFIG.PCW_USB0_RESET_IO {MIO 46} \
  654. CONFIG.PCW_USB0_USB0_IO {<Select>} \
  655. CONFIG.PCW_USB1_RESET_ENABLE {0} \
  656. CONFIG.PCW_USB_RESET_ENABLE {1} \
  657. CONFIG.PCW_USB_RESET_POLARITY {Active Low} \
  658. CONFIG.PCW_USB_RESET_SELECT {<Select>} \
  659. CONFIG.PCW_USE_AXI_NONSECURE {0} \
  660. CONFIG.PCW_USE_CROSS_TRIGGER {0} \
  661. CONFIG.PCW_USE_M_AXI_GP0 {0} \
  662. ] $processing_system7_0
  663. # Create interface connections
  664. connect_bd_intf_net -intf_net processing_system7_0_DDR [get_bd_intf_ports DDR] [get_bd_intf_pins processing_system7_0/DDR]
  665. connect_bd_intf_net -intf_net processing_system7_0_FIXED_IO [get_bd_intf_ports FIXED_IO] [get_bd_intf_pins processing_system7_0/FIXED_IO]
  666. connect_bd_intf_net -intf_net processing_system7_0_GPIO_0 [get_bd_intf_ports GPIO_0_0] [get_bd_intf_pins processing_system7_0/GPIO_0]
  667. # Create port connections
  668. # Create address segments
  669. # Perform GUI Layout
  670. regenerate_bd_layout -layout_string {
  671. "ActiveEmotionalView":"Default View",
  672. "Default View_ScaleFactor":"1.0",
  673. "Default View_TopLeft":"-337,-352",
  674. "ExpandedHierarchyInLayout":"",
  675. "guistr":"# # String gsaved with Nlview 7.0r6 2020-01-29 bk=1.5227 VDI=41 GEI=36 GUI=JA:10.0 non-TLS
  676. # -string -flagsOSRD
  677. preplace port DDR -pg 1 -lvl 2 -x 430 -y -120 -defaultsOSRD
  678. preplace port FIXED_IO -pg 1 -lvl 2 -x 430 -y -100 -defaultsOSRD
  679. preplace port GPIO_0_0 -pg 1 -lvl 2 -x 430 -y -140 -defaultsOSRD
  680. preplace inst processing_system7_0 -pg 1 -lvl 1 -x 210 -y -100 -defaultsOSRD
  681. preplace netloc processing_system7_0_GPIO_0 1 1 1 N -140
  682. preplace netloc processing_system7_0_FIXED_IO 1 1 1 NJ -100
  683. preplace netloc processing_system7_0_DDR 1 1 1 NJ -120
  684. levelinfo -pg 1 0 210 430
  685. pagesize -pg 1 -db -bbox -sgen 0 -220 550 200
  686. "
  687. }
  688. # Restore current instance
  689. current_bd_instance $oldCurInst
  690. validate_bd_design
  691. save_bd_design
  692. close_bd_design $design_name
  693. }
  694. cr_bd_design_1 ""
    INFO: [BD::TCL 103-2010] Currently there is no design <design_1> in project, so creating one...
    Wrote : <C:\AimaginProjects\Zybo\Hardware_Z7000\i2c_demo_new_20230315\project_1\project_1.srcs\sources_1\bd\design_1\design_1.bd>
    create_bd_design: Time (s): cpu = 00:00:04 ; elapsed = 00:00:07 . Memory (MB): peak = 1115.910 ; gain = 0.000
    INFO: [BD::TCL 103-2011] Checking if the following IPs exist in the project's IP catalog:
    xilinx.com:ip:processing_system7:5.5 .
    CRITICAL WARNING: [PSU-1] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.050 . PS DDR interfaces might fail when entering negative DQS skew values.
    CRITICAL WARNING: [PSU-2] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.044 . PS DDR interfaces might fail when entering negative DQS skew values.
    CRITICAL WARNING: [PSU-3] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 has negative value -0.035 . PS DDR interfaces might fail when entering negative DQS skew values.
    CRITICAL WARNING: [PSU-4] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 has negative value -0.100 . PS DDR interfaces might fail when entering negative DQS skew values.
    CRITICAL WARNING: [PSU-1] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.050 . PS DDR interfaces might fail when entering negative DQS skew values.
    CRITICAL WARNING: [PSU-2] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.044 . PS DDR interfaces might fail when entering negative DQS skew values.
    CRITICAL WARNING: [PSU-3] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 has negative value -0.035 . PS DDR interfaces might fail when entering negative DQS skew values.
    CRITICAL WARNING: [PSU-4] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 has negative value -0.100 . PS DDR interfaces might fail when entering negative DQS skew values.
    Wrote : <C:\AimaginProjects\Zybo\Hardware_Z7000\i2c_demo_new_20230315\project_1\project_1.srcs\sources_1\bd\design_1\design_1.bd>
    Wrote : <C:/AimaginProjects/Zybo/Hardware_Z7000/i2c_demo_new_20230315/project_1/project_1.srcs/sources_1/bd/design_1/ui/bd_1f5defd0.ui>
  695. set_property REGISTERED_WITH_MANAGER "1" [get_files design_1.bd ]
  696. set_property SYNTH_CHECKPOINT_MODE "Hierarchical" [get_files design_1.bd ]
  697. if { [get_property IS_LOCKED [ get_files -norecurse design_1.bd] ] == 1 } {
  698. import_files -fileset sources_1 [file normalize "${origin_dir}/project_1/project_1.gen/sources_1/bd/design_1/hdl/design_1_wrapper.vhd" ]
  699. } else {
  700. set wrapper_path [make_wrapper -fileset sources_1 -files [ get_files -norecurse design_1.bd] -top]
  701. add_files -norecurse -fileset sources_1 $wrapper_path
  702. }
    INFO: [BD 41-1662] The design 'design_1.bd' is already validated. Therefore parameter propagation will not be re-run.
    VHDL Output written to : c:/AimaginProjects/Zybo/Hardware_Z7000/i2c_demo_new_20230315/project_1/project_1.gen/sources_1/bd/design_1/synth/design_1.vhd
    VHDL Output written to : c:/AimaginProjects/Zybo/Hardware_Z7000/i2c_demo_new_20230315/project_1/project_1.gen/sources_1/bd/design_1/sim/design_1.vhd
    VHDL Output written to : c:/AimaginProjects/Zybo/Hardware_Z7000/i2c_demo_new_20230315/project_1/project_1.gen/sources_1/bd/design_1/hdl/design_1_wrapper.vhd
    make_wrapper: Time (s): cpu = 00:00:01 ; elapsed = 00:00:06 . Memory (MB): peak = 1400.250 ; gain = 138.207
  703. if {[string equal [get_runs -quiet synth_1] ""]} {
  704. create_run -name synth_1 -part xc7z020clg400-1 -flow {Vivado Synthesis 2020} -strategy "Vivado Synthesis Defaults" -report_strategy {No Reports} -constrset constrs_1
  705. } else {
  706. set_property strategy "Vivado Synthesis Defaults" [get_runs synth_1]
  707. set_property flow "Vivado Synthesis 2020" [get_runs synth_1]
  708. }
  709. set obj [get_runs synth_1]
  710. set_property set_report_strategy_name 1 $obj
  711. set_property report_strategy {Vivado Synthesis Default Reports} $obj
  712. set_property set_report_strategy_name 0 $obj
  713. if { [ string equal [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0] "" ] } {
  714. create_report_config -report_name synth_1_synth_report_utilization_0 -report_type report_utilization:1.0 -steps synth_design -runs synth_1
  715. }
  716. set obj [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0]
  717. if { $obj != "" } {
  718. }
  719. set obj [get_runs synth_1]
  720. set_property -name "strategy" -value "Vivado Synthesis Defaults" -objects $obj
  721. current_run -synthesis [get_runs synth_1]
  722. if {[string equal [get_runs -quiet impl_1] ""]} {
  723. create_run -name impl_1 -part xc7z020clg400-1 -flow {Vivado Implementation 2020} -strategy "Vivado Implementation Defaults" -report_strategy {No Reports} -constrset constrs_1 -parent_run synth_1
  724. } else {
  725. set_property strategy "Vivado Implementation Defaults" [get_runs impl_1]
  726. set_property flow "Vivado Implementation 2020" [get_runs impl_1]
  727. }
  728. set obj [get_runs impl_1]
  729. set_property set_report_strategy_name 1 $obj
  730. set_property report_strategy {Vivado Implementation Default Reports} $obj
  731. set_property set_report_strategy_name 0 $obj
  732. if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0] "" ] } {
  733. create_report_config -report_name impl_1_init_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps init_design -runs impl_1
  734. }
  735. set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0]
  736. if { $obj != "" } {
  737. set_property -name "is_enabled" -value "0" -objects $obj
  738. set_property -name "options.max_paths" -value "10" -objects $obj
  739. }
  740. if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0] "" ] } {
  741. create_report_config -report_name impl_1_opt_report_drc_0 -report_type report_drc:1.0 -steps opt_design -runs impl_1
  742. }
  743. set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0]
  744. if { $obj != "" } {
  745. }
  746. if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0] "" ] } {
  747. create_report_config -report_name impl_1_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps opt_design -runs impl_1
  748. }
  749. set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0]
  750. if { $obj != "" } {
  751. set_property -name "is_enabled" -value "0" -objects $obj
  752. set_property -name "options.max_paths" -value "10" -objects $obj
  753. }
  754. if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0] "" ] } {
  755. create_report_config -report_name impl_1_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps power_opt_design -runs impl_1
  756. }
  757. set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0]
  758. if { $obj != "" } {
  759. set_property -name "is_enabled" -value "0" -objects $obj
  760. set_property -name "options.max_paths" -value "10" -objects $obj
  761. }
  762. if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0] "" ] } {
  763. create_report_config -report_name impl_1_place_report_io_0 -report_type report_io:1.0 -steps place_design -runs impl_1
  764. }
  765. set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0]
  766. if { $obj != "" } {
  767. }
  768. if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0] "" ] } {
  769. create_report_config -report_name impl_1_place_report_utilization_0 -report_type report_utilization:1.0 -steps place_design -runs impl_1
  770. }
  771. set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0]
  772. if { $obj != "" } {
  773. }
  774. if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0] "" ] } {
  775. create_report_config -report_name impl_1_place_report_control_sets_0 -report_type report_control_sets:1.0 -steps place_design -runs impl_1
  776. }
  777. set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0]
  778. if { $obj != "" } {
  779. set_property -name "options.verbose" -value "1" -objects $obj
  780. }
  781. if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0] "" ] } {
  782. create_report_config -report_name impl_1_place_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1
  783. }
  784. set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0]
  785. if { $obj != "" } {
  786. set_property -name "is_enabled" -value "0" -objects $obj
  787. }
  788. if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1] "" ] } {
  789. create_report_config -report_name impl_1_place_report_incremental_reuse_1 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1
  790. }
  791. set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1]
  792. if { $obj != "" } {
  793. set_property -name "is_enabled" -value "0" -objects $obj
  794. }
  795. if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0] "" ] } {
  796. create_report_config -report_name impl_1_place_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps place_design -runs impl_1
  797. }
  798. set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0]
  799. if { $obj != "" } {
  800. set_property -name "is_enabled" -value "0" -objects $obj
  801. set_property -name "options.max_paths" -value "10" -objects $obj
  802. }
  803. if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0] "" ] } {
  804. create_report_config -report_name impl_1_post_place_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_place_power_opt_design -runs impl_1
  805. }
  806. set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0]
  807. if { $obj != "" } {
  808. set_property -name "is_enabled" -value "0" -objects $obj
  809. set_property -name "options.max_paths" -value "10" -objects $obj
  810. }
  811. if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0] "" ] } {
  812. create_report_config -report_name impl_1_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps phys_opt_design -runs impl_1
  813. }
  814. set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0]
  815. if { $obj != "" } {
  816. set_property -name "is_enabled" -value "0" -objects $obj
  817. set_property -name "options.max_paths" -value "10" -objects $obj
  818. }
  819. if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0] "" ] } {
  820. create_report_config -report_name impl_1_route_report_drc_0 -report_type report_drc:1.0 -steps route_design -runs impl_1
  821. }
  822. set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0]
  823. if { $obj != "" } {
  824. }
  825. if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0] "" ] } {
  826. create_report_config -report_name impl_1_route_report_methodology_0 -report_type report_methodology:1.0 -steps route_design -runs impl_1
  827. }
  828. set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0]
  829. if { $obj != "" } {
  830. }
  831. if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0] "" ] } {
  832. create_report_config -report_name impl_1_route_report_power_0 -report_type report_power:1.0 -steps route_design -runs impl_1
  833. }
  834. set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0]
  835. if { $obj != "" } {
  836. }
  837. if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0] "" ] } {
  838. create_report_config -report_name impl_1_route_report_route_status_0 -report_type report_route_status:1.0 -steps route_design -runs impl_1
  839. }
  840. set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0]
  841. if { $obj != "" } {
  842. }
  843. if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0] "" ] } {
  844. create_report_config -report_name impl_1_route_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps route_design -runs impl_1
  845. }
  846. set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0]
  847. if { $obj != "" } {
  848. set_property -name "options.max_paths" -value "10" -objects $obj
  849. }
  850. if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0] "" ] } {
  851. create_report_config -report_name impl_1_route_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps route_design -runs impl_1
  852. }
  853. set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0]
  854. if { $obj != "" } {
  855. }
  856. if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0] "" ] } {
  857. create_report_config -report_name impl_1_route_report_clock_utilization_0 -report_type report_clock_utilization:1.0 -steps route_design -runs impl_1
  858. }
  859. set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0]
  860. if { $obj != "" } {
  861. }
  862. if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0] "" ] } {
  863. create_report_config -report_name impl_1_route_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps route_design -runs impl_1
  864. }
  865. set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0]
  866. if { $obj != "" } {
  867. set_property -name "options.warn_on_violation" -value "1" -objects $obj
  868. }
  869. if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0] "" ] } {
  870. create_report_config -report_name impl_1_post_route_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_route_phys_opt_design -runs impl_1
  871. }
  872. set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0]
  873. if { $obj != "" } {
  874. set_property -name "options.max_paths" -value "10" -objects $obj
  875. set_property -name "options.warn_on_violation" -value "1" -objects $obj
  876. }
  877. if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0] "" ] } {
  878. create_report_config -report_name impl_1_post_route_phys_opt_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps post_route_phys_opt_design -runs impl_1
  879. }
  880. set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0]
  881. if { $obj != "" } {
  882. set_property -name "options.warn_on_violation" -value "1" -objects $obj
  883. }
  884. set obj [get_runs impl_1]
  885. set_property -name "strategy" -value "Vivado Implementation Defaults" -objects $obj
  886. set_property -name "steps.write_bitstream.args.readback_file" -value "0" -objects $obj
  887. set_property -name "steps.write_bitstream.args.verbose" -value "0" -objects $obj
  888. current_run -implementation [get_runs impl_1]
  889. puts "INFO: Project created:${_xil_proj_name_}"
    INFO: Project created:project_1
  890. if {[string equal [get_dashboard_gadgets [ list "drc_1" ] ] ""]} {
  891. create_dashboard_gadget -name {drc_1} -type drc
  892. }
  893. set obj [get_dashboard_gadgets [ list "drc_1" ] ]
  894. set_property -name "reports" -value "impl_1#impl_1_route_report_drc_0" -objects $obj
  895. if {[string equal [get_dashboard_gadgets [ list "methodology_1" ] ] ""]} {
  896. create_dashboard_gadget -name {methodology_1} -type methodology
  897. }
  898. set obj [get_dashboard_gadgets [ list "methodology_1" ] ]
  899. set_property -name "reports" -value "impl_1#impl_1_route_report_methodology_0" -objects $obj
  900. if {[string equal [get_dashboard_gadgets [ list "power_1" ] ] ""]} {
  901. create_dashboard_gadget -name {power_1} -type power
  902. }
  903. set obj [get_dashboard_gadgets [ list "power_1" ] ]
  904. set_property -name "reports" -value "impl_1#impl_1_route_report_power_0" -objects $obj
  905. if {[string equal [get_dashboard_gadgets [ list "timing_1" ] ] ""]} {
  906. create_dashboard_gadget -name {timing_1} -type timing
  907. }
  908. set obj [get_dashboard_gadgets [ list "timing_1" ] ]
  909. set_property -name "reports" -value "impl_1#impl_1_route_report_timing_summary_0" -objects $obj
  910. if {[string equal [get_dashboard_gadgets [ list "utilization_1" ] ] ""]} {
  911. create_dashboard_gadget -name {utilization_1} -type utilization
  912. }
  913. set obj [get_dashboard_gadgets [ list "utilization_1" ] ]
  914. set_property -name "reports" -value "synth_1#synth_1_synth_report_utilization_0" -objects $obj
  915. set_property -name "run.step" -value "synth_design" -objects $obj
  916. set_property -name "run.type" -value "synthesis" -objects $obj
  917. if {[string equal [get_dashboard_gadgets [ list "utilization_2" ] ] ""]} {
  918. create_dashboard_gadget -name {utilization_2} -type utilization
  919. }
  920. set obj [get_dashboard_gadgets [ list "utilization_2" ] ]
  921. set_property -name "reports" -value "impl_1#impl_1_place_report_utilization_0" -objects $obj
  922. move_dashboard_gadget -name {utilization_1} -row 0 -col 0
  923. move_dashboard_gadget -name {power_1} -row 1 -col 0
  924. move_dashboard_gadget -name {drc_1} -row 2 -col 0
  925. move_dashboard_gadget -name {timing_1} -row 0 -col 1
  926. move_dashboard_gadget -name {utilization_2} -row 1 -col 1
  927. move_dashboard_gadget -name {methodology_1} -row 2 -col 1
    update_compile_order -fileset sources_1

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